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-rw-r--r--firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c18
1 files changed, 14 insertions, 4 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c
index ffc6f25a38..b478beceeb 100644
--- a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c
+++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c
@@ -91,6 +91,9 @@ bool button_hold(void)
91 return (__gpio_get_pin(PIN_BTN_HOLD) ? true : false); 91 return (__gpio_get_pin(PIN_BTN_HOLD) ? true : false);
92} 92}
93 93
94/* NOTE: Due to how this is wired, button combinations are not allowed
95 unless one of the two buttons is the POWER
96*/
94int button_read_device(void) 97int button_read_device(void)
95{ 98{
96#ifndef BOOTLOADER 99#ifndef BOOTLOADER
@@ -104,8 +107,10 @@ int button_read_device(void)
104 int btn = BUTTON_NONE; 107 int btn = BUTTON_NONE;
105 bool gpio_btn = (__gpio_get_pin(PIN_BTN_POWER) ? false : true); 108 bool gpio_btn = (__gpio_get_pin(PIN_BTN_POWER) ? false : true);
106 109
107 REG_SADC_ADCFG = ADCFG_VBAT_SEL + ADCFG_CMD_AUX(1); 110 /* Don't initiate a new request if we have one pending */
108 REG_SADC_ADENA = ADENA_VBATEN + ADENA_AUXEN; 111 if (!(REG_SADC_ADENA & (ADENA_VBATEN | ADENA_AUXEN))) {
112 REG_SADC_ADENA = ADENA_VBATEN | ADENA_AUXEN;
113 }
109 114
110#ifndef BOOTLOADER 115#ifndef BOOTLOADER
111 if (hold_button != hold_button_old) { 116 if (hold_button != hold_button_old) {
@@ -192,6 +197,11 @@ int _battery_voltage(void)
192 return (bat_val*BATTERY_SCALE_FACTOR)>>10; 197 return (bat_val*BATTERY_SCALE_FACTOR)>>10;
193} 198}
194 199
200/* 12MHz XTAL
201 /61 = 196 MHz base clock (max is 200, err on the side of safety)
202 /(1+1) = 98.4KHz "us_clk (ie ~10us/tick)
203 /(199+1) = 983.6KHz "ms_clk" (ie ~1ms/tick)
204*/
195void adc_init(void) 205void adc_init(void)
196{ 206{
197 bat_val = 0xfff; 207 bat_val = 0xfff;
@@ -202,8 +212,8 @@ void adc_init(void)
202 mdelay(70); 212 mdelay(70);
203 REG_SADC_ADSTATE = 0; 213 REG_SADC_ADSTATE = 0;
204 REG_SADC_ADCTRL = ADCTRL_MASK_ALL - ADCTRL_ARDYM - ADCTRL_VRDYM; 214 REG_SADC_ADCTRL = ADCTRL_MASK_ALL - ADCTRL_ARDYM - ADCTRL_VRDYM;
205 REG_SADC_ADCFG = ADCFG_VBAT_SEL + ADCFG_CMD_AUX(1); 215 REG_SADC_ADCFG = ADCFG_VBAT_SEL | ADCFG_CMD_AUX(1); /* VBAT_SEL is undocumented but required! */
206 REG_SADC_ADCLK = (4 << 16) | (1 << 8) | 59; /* 200KHz */ 216 REG_SADC_ADCLK = (199 << 16) | (1 << 8) | 61;
207 system_enable_irq(IRQ_SADC); 217 system_enable_irq(IRQ_SADC);
208} 218}
209 219