diff options
Diffstat (limited to 'firmware/target/mips')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index a8e40e4e31..ff87e5ad9e 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c | |||
@@ -503,6 +503,9 @@ static void pll0_init(unsigned int freq) | |||
503 | /* Init MSC clock; shoot for 48MHz base clock. */ | 503 | /* Init MSC clock; shoot for 48MHz base clock. */ |
504 | REG_CPM_MSCCDR = MSCCDR_MCS | ((freq / 48000000) - 1); | 504 | REG_CPM_MSCCDR = MSCCDR_MCS | ((freq / 48000000) - 1); |
505 | 505 | ||
506 | /* Clock LCD clock as low as possible here */ | ||
507 | __cpm_set_pixdiv(2048 -1); | ||
508 | |||
506 | /* init PLL */ | 509 | /* init PLL */ |
507 | REG_CPM_CPCCR = cfcr; | 510 | REG_CPM_CPCCR = cfcr; |
508 | REG_CPM_CPPCR0 = plcr1; | 511 | REG_CPM_CPPCR0 = plcr1; |