diff options
Diffstat (limited to 'firmware/target/mips')
6 files changed, 134 insertions, 116 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/crt0.S b/firmware/target/mips/ingenic_jz47xx/crt0.S index 97e01d8566..5cfd49141a 100644 --- a/firmware/target/mips/ingenic_jz47xx/crt0.S +++ b/firmware/target/mips/ingenic_jz47xx/crt0.S | |||
@@ -66,17 +66,16 @@ _start: | |||
66 | 66 | ||
67 | li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \ | 67 | li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \ |
68 | | M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \ | 68 | | M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \ |
69 | | M_StatusIM2 | M_StatusERL | M_StatusSM) | 69 | | M_StatusIM2 | M_StatusERL) |
70 | /* | 70 | /* |
71 | BEV = Enable Boot Exception Vectors | 71 | BEV = Enable Boot Exception Vectors |
72 | IMx = Interrupt mask | 72 | IMx = Interrupt mask |
73 | ERL = Denotes error level | 73 | ERL = Denotes error level |
74 | SM = Supervisor Mode | ||
75 | */ | 74 | */ |
76 | mtc0 t0, C0_STATUS | 75 | mtc0 t0, C0_STATUS |
77 | 76 | ||
78 | li t1, M_CauseIV | 77 | li t0, M_CauseIV |
79 | mtc0 t1, C0_CAUSE | 78 | mtc0 t0, C0_CAUSE |
80 | 79 | ||
81 | /* | 80 | /* |
82 | ---------------------------------------------------- | 81 | ---------------------------------------------------- |
@@ -85,7 +84,7 @@ _start: | |||
85 | */ | 84 | */ |
86 | li t0, 3 // enable cache for kseg0 accesses | 85 | li t0, 3 // enable cache for kseg0 accesses |
87 | mtc0 t0, C0_CONFIG // CONFIG reg | 86 | mtc0 t0, C0_CONFIG // CONFIG reg |
88 | la t0, 0x80000000 // an idx op should use a unmappable address | 87 | la t0, 0x80000000 // an idx op should use an unmappable address |
89 | ori t1, t0, 0x4000 // 16kB cache | 88 | ori t1, t0, 0x4000 // 16kB cache |
90 | mtc0 zero, C0_TAGLO // TAGLO reg | 89 | mtc0 zero, C0_TAGLO // TAGLO reg |
91 | mtc0 zero, C0_TAGHI // TAGHI reg | 90 | mtc0 zero, C0_TAGHI // TAGHI reg |
@@ -215,25 +214,26 @@ real_exception_handler: | |||
215 | sw v1, 0x64(sp) | 214 | sw v1, 0x64(sp) |
216 | sw v0, 0x68(sp) | 215 | sw v0, 0x68(sp) |
217 | sw $1, 0x6C(sp) | 216 | sw $1, 0x6C(sp) |
218 | mflo t0 # Move From LO | 217 | mflo k0 # Move From LO |
219 | nop | 218 | nop |
220 | sw t0, 0x70(sp) | 219 | sw k0, 0x70(sp) |
221 | mfhi t0 # Move From HI | 220 | mfhi k0 # Move From HI |
222 | nop | 221 | nop |
223 | sw t0, 0x74(sp) | 222 | sw k0, 0x74(sp) |
224 | mfc0 t0, C0_STATUS # Status register | 223 | mfc0 k0, C0_STATUS # Status register |
225 | sll zero, 1 | 224 | sll zero, 1 |
226 | sll zero, 1 | 225 | sll zero, 1 |
227 | sll zero, 1 | 226 | sll zero, 1 |
228 | sll zero, 1 | 227 | sll zero, 1 |
229 | sw t0, 0x78(sp) | 228 | sw k0, 0x78(sp) |
230 | mfc0 t0, C0_EPC # Exception Program Counter | 229 | mfc0 k0, C0_EPC # Exception Program Counter |
231 | sll zero, 1 | 230 | sll zero, 1 |
232 | sll zero, 1 | 231 | sll zero, 1 |
233 | sll zero, 1 | 232 | sll zero, 1 |
234 | sll zero, 1 | 233 | sll zero, 1 |
235 | sw t0, 0x7C(sp) | 234 | sw k0, 0x7C(sp) |
236 | li k1, 0x7C | 235 | |
236 | li k1, M_CauseExcCode | ||
237 | mfc0 k0, C0_CAUSE # C0_CAUSE of last exception | 237 | mfc0 k0, C0_CAUSE # C0_CAUSE of last exception |
238 | and k0, k1 | 238 | and k0, k1 |
239 | beq zero, k0, _int | 239 | beq zero, k0, _int |
@@ -273,7 +273,7 @@ _int: | |||
273 | lw a0, 0x60(sp) | 273 | lw a0, 0x60(sp) |
274 | lw v1, 0x64(sp) | 274 | lw v1, 0x64(sp) |
275 | lw v0, 0x68(sp) | 275 | lw v0, 0x68(sp) |
276 | lw v1, 0x6C(sp) | 276 | lw $1, 0x6C(sp) |
277 | lw k0, 0x70(sp) | 277 | lw k0, 0x70(sp) |
278 | mtlo k0 # Move To LO | 278 | mtlo k0 # Move To LO |
279 | nop | 279 | nop |
@@ -313,7 +313,57 @@ _exception: | |||
313 | sll zero, 1 | 313 | sll zero, 1 |
314 | sll zero, 1 | 314 | sll zero, 1 |
315 | sll zero, 1 | 315 | sll zero, 1 |
316 | la k0, exception_handler | 316 | jal exception_handler |
317 | jr k0 | 317 | nop |
318 | lw ra, 0(sp) | ||
319 | lw fp, 4(sp) | ||
320 | sw gp, 8(sp) | ||
321 | lw t9, 0xC(sp) | ||
322 | lw t8, 0x10(sp) | ||
323 | lw s7, 0x14(sp) | ||
324 | lw s6, 0x18(sp) | ||
325 | lw s5, 0x1C(sp) | ||
326 | lw s4, 0x20(sp) | ||
327 | lw s3, 0x24(sp) | ||
328 | lw s2, 0x28(sp) | ||
329 | lw s1, 0x2C(sp) | ||
330 | lw s0, 0x30(sp) | ||
331 | lw t7, 0x34(sp) | ||
332 | lw t6, 0x38(sp) | ||
333 | lw t5, 0x3C(sp) | ||
334 | lw t4, 0x40(sp) | ||
335 | lw t3, 0x44(sp) | ||
336 | lw t2, 0x48(sp) | ||
337 | lw t1, 0x4C(sp) | ||
338 | lw t0, 0x50(sp) | ||
339 | lw a3, 0x54(sp) | ||
340 | lw a2, 0x58(sp) | ||
341 | lw a1, 0x5C(sp) | ||
342 | lw a0, 0x60(sp) | ||
343 | lw v1, 0x64(sp) | ||
344 | lw v0, 0x68(sp) | ||
345 | lw $1, 0x6C(sp) | ||
346 | lw k0, 0x70(sp) | ||
347 | mtlo k0 # Move To LO | ||
348 | nop | ||
349 | lw k0, 0x74(sp) | ||
350 | mthi k0 # Move To HI | ||
351 | nop | ||
352 | lw k0, 0x78(sp) | ||
353 | nop | ||
354 | mtc0 k0, C0_STATUS # Status register | ||
355 | sll zero, 1 | ||
356 | sll zero, 1 | ||
357 | sll zero, 1 | ||
358 | sll zero, 1 | ||
359 | lw k0, 0x7C(sp) | ||
360 | nop | ||
361 | mtc0 k0, C0_EPC # Exception Program Counter | ||
362 | sll zero, 1 | ||
363 | sll zero, 1 | ||
364 | sll zero, 1 | ||
365 | sll zero, 1 | ||
366 | addiu sp, 0x80 | ||
367 | eret # Exception Return | ||
318 | nop | 368 | nop |
319 | .set reorder | 369 | .set reorder |
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c index 6bb7db8d9b..90ecfc6a3a 100644 --- a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c | |||
@@ -68,7 +68,7 @@ void lcd_update_rect(int x, int y, int width, int height) | |||
68 | | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */ | 68 | | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */ |
69 | REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */ | 69 | REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */ |
70 | 70 | ||
71 | dma_cache_wback_inv((unsigned long)&lcd_framebuffer[y][x], width*height); | 71 | __dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size */ |
72 | 72 | ||
73 | REG_DMAC_DMACR = DMAC_DMACR_DMAE; | 73 | REG_DMAC_DMACR = DMAC_DMACR_DMAE; |
74 | 74 | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c index 98fa8e7a20..3846987026 100644 --- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c | |||
@@ -24,14 +24,14 @@ | |||
24 | #include "r61509.h" | 24 | #include "r61509.h" |
25 | #include "lcd-target.h" | 25 | #include "lcd-target.h" |
26 | 26 | ||
27 | #define PIN_CS_N (32*1+17) /* Chip select */ | 27 | #define PIN_CS_N (32*1+17) /* Chip select */ |
28 | #define PIN_RESET_N (32*1+18) /* Reset */ | 28 | #define PIN_RESET_N (32*1+18) /* Reset */ |
29 | 29 | ||
30 | #define my__gpio_as_lcd_16bit() \ | 30 | #define my__gpio_as_lcd_16bit() \ |
31 | do { \ | 31 | do { \ |
32 | REG_GPIO_PXFUNS(2) = 0x001cffff; \ | 32 | REG_GPIO_PXFUNS(2) = 0x001cffff; \ |
33 | REG_GPIO_PXSELC(2) = 0x001cffff; \ | 33 | REG_GPIO_PXSELC(2) = 0x001cffff; \ |
34 | REG_GPIO_PXPES(2) = 0x001cffff; \ | 34 | REG_GPIO_PXPES(2) = 0x001cffff; \ |
35 | } while (0) | 35 | } while (0) |
36 | 36 | ||
37 | 37 | ||
@@ -45,12 +45,12 @@ static void _display_pin_init(void) | |||
45 | __gpio_as_output(PIN_RESET_N); | 45 | __gpio_as_output(PIN_RESET_N); |
46 | __gpio_clear_pin(PIN_CS_N); | 46 | __gpio_clear_pin(PIN_CS_N); |
47 | 47 | ||
48 | __gpio_set_pin(PIN_RESET_N); | 48 | __gpio_set_pin(PIN_RESET_N); |
49 | DELAY; | 49 | DELAY; |
50 | __gpio_clear_pin(PIN_RESET_N); | 50 | __gpio_clear_pin(PIN_RESET_N); |
51 | DELAY; | 51 | DELAY; |
52 | __gpio_set_pin(PIN_RESET_N); | 52 | __gpio_set_pin(PIN_RESET_N); |
53 | DELAY; | 53 | DELAY; |
54 | } | 54 | } |
55 | 55 | ||
56 | #define WAIT_ON_SLCD while(REG_SLCD_STATE & SLCD_STATE_BUSY); | 56 | #define WAIT_ON_SLCD while(REG_SLCD_STATE & SLCD_STATE_BUSY); |
@@ -189,7 +189,7 @@ static void _display_off(void) | |||
189 | static void _set_lcd_bus(void) | 189 | static void _set_lcd_bus(void) |
190 | { | 190 | { |
191 | REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK; | 191 | REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK; |
192 | REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD; | 192 | REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD; |
193 | 193 | ||
194 | REG_SLCD_CFG = (SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_16 | SLCD_CFG_CWIDTH_16BIT | 194 | REG_SLCD_CFG = (SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_16 | SLCD_CFG_CWIDTH_16BIT |
195 | | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING | 195 | | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING |
@@ -200,17 +200,17 @@ static void _set_lcd_bus(void) | |||
200 | 200 | ||
201 | static void _set_lcd_clock(void) | 201 | static void _set_lcd_clock(void) |
202 | { | 202 | { |
203 | unsigned int val; | 203 | unsigned int val; |
204 | int pll_div; | 204 | int pll_div; |
205 | 205 | ||
206 | __cpm_stop_lcd(); | 206 | __cpm_stop_lcd(); |
207 | pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source, 0:pllout/2 1: pllout */ | 207 | pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source, 0:pllout/2 1: pllout */ |
208 | pll_div = pll_div ? 1 : 2 ; | 208 | pll_div = pll_div ? 1 : 2 ; |
209 | val = ( __cpm_get_pllout()/pll_div ) / 336000000; | 209 | val = ( __cpm_get_pllout()/pll_div ) / 336000000; |
210 | val--; | 210 | val--; |
211 | if ( val > 0x1ff ) | 211 | if ( val > 0x1ff ) |
212 | val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */ | 212 | val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */ |
213 | __cpm_set_pixdiv(val); | 213 | __cpm_set_pixdiv(val); |
214 | __cpm_start_lcd(); | 214 | __cpm_start_lcd(); |
215 | } | 215 | } |
216 | 216 | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c index 0f11782d3f..dd169c3a44 100644 --- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c | |||
@@ -122,13 +122,16 @@ int button_read_device(int *data) | |||
122 | ret |= BUTTON_POWER; | 122 | ret |= BUTTON_POWER; |
123 | } | 123 | } |
124 | 124 | ||
125 | if(pendown_flag) | 125 | if(data != NULL) |
126 | { | 126 | { |
127 | *data = touch_to_pixels(stable_x_pos, stable_y_pos); | 127 | if(pendown_flag) |
128 | ret |= BUTTON_TOUCH; | 128 | { |
129 | *data = touch_to_pixels(stable_x_pos, stable_y_pos); | ||
130 | ret |= BUTTON_TOUCH; | ||
131 | } | ||
132 | else | ||
133 | *data = 0; | ||
129 | } | 134 | } |
130 | else | ||
131 | *data = 0; | ||
132 | 135 | ||
133 | return ret; | 136 | return ret; |
134 | } | 137 | } |
@@ -199,7 +202,7 @@ void SADC(void) | |||
199 | 202 | ||
200 | xData = (dat >> 0) & 0xfff; | 203 | xData = (dat >> 0) & 0xfff; |
201 | yData = (dat >> 16) & 0xfff; | 204 | yData = (dat >> 16) & 0xfff; |
202 | 205 | ||
203 | dat = REG_SADC_TSDAT; | 206 | dat = REG_SADC_TSDAT; |
204 | tsz1Data = (dat >> 0) & 0xfff; | 207 | tsz1Data = (dat >> 0) & 0xfff; |
205 | tsz2Data = (dat >> 16) & 0xfff; | 208 | tsz2Data = (dat >> 16) & 0xfff; |
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c index 61be6c60de..1a41723ffc 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c | |||
@@ -324,7 +324,7 @@ static int get_irq_number(void) | |||
324 | 324 | ||
325 | void intr_handler(void) | 325 | void intr_handler(void) |
326 | { | 326 | { |
327 | irq = get_irq_number(); | 327 | int irq = get_irq_number(); |
328 | if(irq < 0) | 328 | if(irq < 0) |
329 | return; | 329 | return; |
330 | 330 | ||
@@ -361,7 +361,7 @@ static char* parse_exception(unsigned int cause) | |||
361 | } | 361 | } |
362 | 362 | ||
363 | void exception_handler(void* stack_ptr, unsigned int cause, unsigned int epc) | 363 | void exception_handler(void* stack_ptr, unsigned int cause, unsigned int epc) |
364 | { | 364 | { |
365 | panicf("Exception occurred: %s [0x%08x] at 0x%08x (stack at 0x%08x)", parse_exception(cause), cause, epc, (unsigned int)stack_ptr); | 365 | panicf("Exception occurred: %s [0x%08x] at 0x%08x (stack at 0x%08x)", parse_exception(cause), cause, epc, (unsigned int)stack_ptr); |
366 | } | 366 | } |
367 | 367 | ||
@@ -457,23 +457,6 @@ void __icache_invalidate_all(void) | |||
457 | { | 457 | { |
458 | unsigned int i; | 458 | unsigned int i; |
459 | 459 | ||
460 | /* | ||
461 | do | ||
462 | { | ||
463 | unsigned long __k0_addr; | ||
464 | |||
465 | __asm__ __volatile__( | ||
466 | "la %0, 1f \n" | ||
467 | "or %0, %0, %1 \n" | ||
468 | "jr %0 \n" | ||
469 | "nop \n" | ||
470 | "1: nop \n" | ||
471 | : "=&r"(__k0_addr) | ||
472 | : "r" (0x20000000) | ||
473 | ); | ||
474 | } while(0); | ||
475 | */ | ||
476 | |||
477 | asm volatile (".set noreorder \n" | 460 | asm volatile (".set noreorder \n" |
478 | ".set mips32 \n" | 461 | ".set mips32 \n" |
479 | "mtc0 $0, $28 \n" /* TagLo */ | 462 | "mtc0 $0, $28 \n" /* TagLo */ |
@@ -484,34 +467,16 @@ void __icache_invalidate_all(void) | |||
484 | for(i=KSEG0; i<KSEG0+CACHE_SIZE; i+=CACHE_LINE_SIZE) | 467 | for(i=KSEG0; i<KSEG0+CACHE_SIZE; i+=CACHE_LINE_SIZE) |
485 | __CACHE_OP(Index_Store_Tag_I, i); | 468 | __CACHE_OP(Index_Store_Tag_I, i); |
486 | 469 | ||
487 | /* | 470 | /* invalidate btb */ |
488 | do | 471 | asm volatile ( |
489 | { | 472 | ".set mips32 \n" |
490 | unsigned long __k0_addr; | 473 | "mfc0 %0, $16, 7 \n" |
491 | __asm__ __volatile__( | 474 | "nop \n" |
492 | "nop;nop;nop;nop;nop;nop;nop \n" | 475 | "ori %0, 2 \n" |
493 | "la %0, 1f \n" | 476 | "mtc0 %0, $16, 7 \n" |
494 | "jr %0 \n" | 477 | ".set mips0 \n" |
495 | "nop \n" | 478 | : |
496 | "1: nop \n" | 479 | : "r" (i)); |
497 | : "=&r" (__k0_addr) | ||
498 | ); | ||
499 | } while(0); | ||
500 | */ | ||
501 | |||
502 | do | ||
503 | { | ||
504 | unsigned long tmp; | ||
505 | __asm__ __volatile__( | ||
506 | ".set mips32 \n" | ||
507 | "mfc0 %0, $16, 7 \n" /* Config */ | ||
508 | "nop \n" | ||
509 | "ori %0, 2 \n" | ||
510 | "mtc0 %0, $16, 7 \n" /* Config */ | ||
511 | "nop \n" | ||
512 | ".set mips0 \n" | ||
513 | : "=&r" (tmp)); | ||
514 | } while(0); | ||
515 | } | 480 | } |
516 | 481 | ||
517 | void __dcache_invalidate_all(void) | 482 | void __dcache_invalidate_all(void) |
@@ -657,13 +622,14 @@ static void tlb_init(void) | |||
657 | 622 | ||
658 | void tlb_refill_handler(void) | 623 | void tlb_refill_handler(void) |
659 | { | 624 | { |
660 | panicf("TLB refill handler! [0x%x] [0x%lx]", read_c0_badvaddr(), read_c0_epc()); | 625 | panicf("TLB refill handler at 0x%08lx! [0x%x]", read_c0_epc(), read_c0_badvaddr()); |
661 | } | 626 | } |
662 | 627 | ||
663 | static void tlb_call_refill(void) | 628 | static void tlb_call_refill(void) |
664 | { | 629 | { |
665 | asm("la $8, tlb_refill_handler \n" | 630 | asm("la $8, tlb_refill_handler \n" |
666 | "jr $8 \n"); | 631 | "jr $8 \n" |
632 | ); | ||
667 | } | 633 | } |
668 | 634 | ||
669 | extern int main(void); | 635 | extern int main(void); |
@@ -687,18 +653,18 @@ void system_main(void) | |||
687 | __dcache_writeback_all(); | 653 | __dcache_writeback_all(); |
688 | __icache_invalidate_all(); | 654 | __icache_invalidate_all(); |
689 | 655 | ||
690 | write_c0_status(1 << 28 | 1 << 10 | 1 << 3); /* Enable CP | Mask interrupt 2 | Supervisor mode */ | 656 | write_c0_status(1 << 28 | 1 << 10 ); /* Enable CP | Mask interrupt 2 */ |
691 | 657 | ||
692 | /* Disable all interrupts */ | 658 | /* Disable all interrupts */ |
693 | for(i=0; i<IRQ_MAX; i++) | 659 | for(i=0; i<IRQ_MAX; i++) |
694 | dis_irq(i); | 660 | dis_irq(i); |
695 | 661 | ||
696 | //tlb_init(); | 662 | tlb_init(); |
697 | |||
698 | sti(); | ||
699 | 663 | ||
700 | detect_clock(); | 664 | detect_clock(); |
701 | 665 | ||
666 | sti(); | ||
667 | |||
702 | main(); | 668 | main(); |
703 | 669 | ||
704 | while(1); | 670 | while(1); |
diff --git a/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c b/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c index 92a2f3b801..cf107397e3 100644 --- a/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c | |||
@@ -824,25 +824,21 @@ void usbHandleStandDevReq(u8 *buf) | |||
824 | 824 | ||
825 | extern char printfbuf[256]; | 825 | extern char printfbuf[256]; |
826 | 826 | ||
827 | int GET_CUP_INFO_Handle() | ||
828 | { | ||
829 | HW_SendPKT(0, printfbuf, 64); | ||
830 | udc_state = IDLE; | ||
831 | return 0; | ||
832 | } | ||
833 | |||
834 | void usbHandleVendorReq(u8 *buf) | 827 | void usbHandleVendorReq(u8 *buf) |
835 | { | 828 | { |
836 | int ret_state; | 829 | int ret_state, i; |
837 | USB_DeviceRequest *dreq = (USB_DeviceRequest *)buf; | 830 | USB_DeviceRequest *dreq = (USB_DeviceRequest *)buf; |
838 | switch (dreq->bRequest) { | 831 | switch (dreq->bRequest) |
839 | case 0xAB: | 832 | { |
840 | ret_state=GET_CUP_INFO_Handle(); | 833 | case 0xAB: |
841 | break; | 834 | //for(i=0; i<256; i+=64) |
842 | case 0x12: | 835 | HW_SendPKT(0, printfbuf, 64); |
843 | HW_SendPKT(0, "TEST", 4); | 836 | udc_state = IDLE; |
844 | udc_state = IDLE; | 837 | break; |
845 | break; | 838 | case 0x12: |
839 | HW_SendPKT(0, "TEST", 4); | ||
840 | udc_state = IDLE; | ||
841 | break; | ||
846 | } | 842 | } |
847 | } | 843 | } |
848 | 844 | ||
@@ -1032,6 +1028,9 @@ void __udc_start(void) | |||
1032 | system_enable_irq(IRQ_UDC); | 1028 | system_enable_irq(IRQ_UDC); |
1033 | } | 1029 | } |
1034 | 1030 | ||
1035 | void usb_init_device(void){} | 1031 | void usb_init_device(void) |
1032 | { | ||
1033 | __udc_start(); | ||
1034 | } | ||
1036 | 1035 | ||
1037 | #endif | 1036 | #endif |