diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/system-x1000.c')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/system-x1000.c | 38 |
1 files changed, 2 insertions, 36 deletions
diff --git a/firmware/target/mips/ingenic_x1000/system-x1000.c b/firmware/target/mips/ingenic_x1000/system-x1000.c index 54513cffb2..d841a274ed 100644 --- a/firmware/target/mips/ingenic_x1000/system-x1000.c +++ b/firmware/target/mips/ingenic_x1000/system-x1000.c | |||
@@ -40,40 +40,6 @@ int __cpu_idle_cur = 0; | |||
40 | uint32_t __cpu_idle_ticks = 0; | 40 | uint32_t __cpu_idle_ticks = 0; |
41 | uint32_t __cpu_idle_reftick = 0; | 41 | uint32_t __cpu_idle_reftick = 0; |
42 | 42 | ||
43 | static void system_init_clk(void) | ||
44 | { | ||
45 | /* Gate all clocks except CPU/bus/memory/RTC */ | ||
46 | REG_CPM_CLKGR = ~jz_orm(CPM_CLKGR, CPU_BIT, DDR, AHB0, APB0, RTC); | ||
47 | |||
48 | /* Switch to EXCLK */ | ||
49 | clk_set_ccr_mux(CLKMUX_SCLK_A(EXCLK) | CLKMUX_CPU(SCLK_A) | | ||
50 | CLKMUX_AHB0(SCLK_A) | CLKMUX_AHB2(SCLK_A)); | ||
51 | clk_set_ccr_div(1, 1, 1, 1, 1); | ||
52 | |||
53 | #ifdef FIIO_M3K | ||
54 | /* Nominal clock configuration | ||
55 | * --------------------------- | ||
56 | * APLL at 1 GHz, MPLL disabled | ||
57 | * CPU at 1 GHz, L2 cache at 500 MHz | ||
58 | * AHB0 and AHB2 at 200 MHz | ||
59 | * PCLK at 100 MHz | ||
60 | * DDR at 200 MHz | ||
61 | */ | ||
62 | jz_writef(CPM_APCR, BS(1), PLLM(41), PLLN(0), PLLOD(0), ENABLE(1)); | ||
63 | while(jz_readf(CPM_APCR, ON) == 0); | ||
64 | |||
65 | clk_set_ccr_div(1, 2, 5, 5, 10); | ||
66 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | CLKMUX_CPU(SCLK_A) | | ||
67 | CLKMUX_AHB0(SCLK_A) | CLKMUX_AHB2(SCLK_A)); | ||
68 | clk_set_ddr(X1000_CLK_SCLK_A, 5); | ||
69 | |||
70 | /* Shut off MPLL, since nobody should be using it now */ | ||
71 | jz_writef(CPM_MPCR, ENABLE(0)); | ||
72 | #else | ||
73 | # error "Please define system clock configuration for target" | ||
74 | #endif | ||
75 | } | ||
76 | |||
77 | /* Prepare the CPU to process interrupts, but don't enable them yet */ | 43 | /* Prepare the CPU to process interrupts, but don't enable them yet */ |
78 | static void system_init_irq(void) | 44 | static void system_init_irq(void) |
79 | { | 45 | { |
@@ -94,8 +60,8 @@ static void system_init_irq(void) | |||
94 | /* First thing called from Rockbox main() */ | 60 | /* First thing called from Rockbox main() */ |
95 | void system_init(void) | 61 | void system_init(void) |
96 | { | 62 | { |
97 | /* Setup system clocks */ | 63 | /* Gate all clocks except CPU/bus/memory/RTC */ |
98 | system_init_clk(); | 64 | REG_CPM_CLKGR = ~jz_orm(CPM_CLKGR, CPU_BIT, DDR, AHB0, APB0, RTC); |
99 | 65 | ||
100 | /* Ungate timers and turn them all off by default */ | 66 | /* Ungate timers and turn them all off by default */ |
101 | jz_writef(CPM_CLKGR, TCU(0), OST(0)); | 67 | jz_writef(CPM_CLKGR, TCU(0), OST(0)); |