1 files changed, 11 insertions, 12 deletions

diff --git a/firmware/target/mips/ingenic_x1000/spl.lds b/firmware/target/mips/ingenic_x1000/spl.lds
index 39b5939a6a..e8bf9d4700 100644
--- a/firmware/target/mips/ingenic_x1000/spl.lds
+++ b/firmware/target/mips/ingenic_x1000/spl.lds
@@ -1,23 +1,22 @@
 #include "config.h"
+#include "cpu.h"
 
 OUTPUT_FORMAT("elf32-littlemips")
 OUTPUT_ARCH(MIPS)
 ENTRY(_start)
 STARTUP(target/mips/ingenic_x1000/crt0.o)
 
-#define DRAMORIG 0x80000000
-#define DRAMSIZE (MEMORYSIZE * 0x100000)
-#define USED_DRAM 16K
-
-/* TCSM is 16 KiB and is mapped starting at address 0xf4000000.
- *
- * The SPL is loaded to TCSM + 0x1000. The area below that is stack space.
- * The first 2 KiB of SPL is just headers. The code begins at TCSM + 0x1800.
- * The maskrom will jump to that address (via jalr) after loading the SPL.
- */
 MEMORY {
-    TCSM : ORIGIN = 0xf4001800, LENGTH = 0x2800
-    DRAM : ORIGIN = DRAMORIG + DRAMSIZE - USED_DRAM, LENGTH = USED_DRAM
+    /* First 4k of TCSM is used by mask ROM for stack + variables,
+     * and the next 2k are occupied by SPL header */
+    TCSM : ORIGIN = X1000_TCSM_BASE + 0x1800,
+           LENGTH = X1000_TCSM_SIZE - 0x1800
+
+    /* Small area of DRAM is required for NAND bounce buffers,
+     * though not strictly necessary as ECC isn't really practical
+     * this early in the boot */
+    DRAM : ORIGIN = X1000_DRAM_END - 16K,
+           LENGTH = 16K
 }
 
 SECTIONS