diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/nand-x1000.c')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/nand-x1000.c | 35 |
1 files changed, 11 insertions, 24 deletions
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c index e22c639b8f..896ac97d28 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.c +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c | |||
@@ -31,8 +31,6 @@ const struct nand_chip supported_nand_chips[] = { | |||
31 | /* ATO25D1GA */ | 31 | /* ATO25D1GA */ |
32 | .mf_id = 0x9b, | 32 | .mf_id = 0x9b, |
33 | .dev_id = 0x12, | 33 | .dev_id = 0x12, |
34 | .row_cycles = 3, | ||
35 | .col_cycles = 2, | ||
36 | .log2_ppb = 6, /* 64 pages */ | 34 | .log2_ppb = 6, /* 64 pages */ |
37 | .page_size = 2048, | 35 | .page_size = 2048, |
38 | .oob_size = 64, | 36 | .oob_size = 64, |
@@ -46,6 +44,11 @@ const struct nand_chip supported_nand_chips[] = { | |||
46 | STA_TYPE_V(1BYTE), CMD_TYPE_V(8BITS), | 44 | STA_TYPE_V(1BYTE), CMD_TYPE_V(8BITS), |
47 | SMP_DELAY(1)), | 45 | SMP_DELAY(1)), |
48 | .flags = NAND_CHIPFLAG_QUAD | NAND_CHIPFLAG_HAS_QE_BIT, | 46 | .flags = NAND_CHIPFLAG_QUAD | NAND_CHIPFLAG_HAS_QE_BIT, |
47 | .cmd_page_read = NANDCMD_PAGE_READ(3), | ||
48 | .cmd_program_execute = NANDCMD_PROGRAM_EXECUTE(3), | ||
49 | .cmd_block_erase = NANDCMD_BLOCK_ERASE(3), | ||
50 | .cmd_read_cache = NANDCMD_READ_CACHE_x4(2), | ||
51 | .cmd_program_load = NANDCMD_PROGRAM_LOAD_x4(2), | ||
49 | }, | 52 | }, |
50 | #else | 53 | #else |
51 | { 0 }, | 54 | { 0 }, |
@@ -127,22 +130,6 @@ static void setup_chip_data(struct nand_drv* drv) | |||
127 | drv->fpage_size = drv->chip->page_size + drv->chip->oob_size; | 130 | drv->fpage_size = drv->chip->page_size + drv->chip->oob_size; |
128 | } | 131 | } |
129 | 132 | ||
130 | static void setup_chip_commands(struct nand_drv* drv) | ||
131 | { | ||
132 | /* Select commands appropriate for the chip */ | ||
133 | drv->cmd_page_read = NANDCMD_PAGE_READ(drv->chip->row_cycles); | ||
134 | drv->cmd_program_execute = NANDCMD_PROGRAM_EXECUTE(drv->chip->row_cycles); | ||
135 | drv->cmd_block_erase = NANDCMD_BLOCK_ERASE(drv->chip->row_cycles); | ||
136 | |||
137 | if(drv->chip->flags & NAND_CHIPFLAG_QUAD) { | ||
138 | drv->cmd_read_cache = NANDCMD_READ_CACHE_x4(drv->chip->col_cycles); | ||
139 | drv->cmd_program_load = NANDCMD_PROGRAM_LOAD_x4(drv->chip->col_cycles); | ||
140 | } else { | ||
141 | drv->cmd_read_cache = NANDCMD_READ_CACHE(drv->chip->col_cycles); | ||
142 | drv->cmd_program_load = NANDCMD_PROGRAM_LOAD(drv->chip->col_cycles); | ||
143 | } | ||
144 | } | ||
145 | |||
146 | static void setup_chip_registers(struct nand_drv* drv) | 133 | static void setup_chip_registers(struct nand_drv* drv) |
147 | { | 134 | { |
148 | /* Set chip registers to enter normal operation */ | 135 | /* Set chip registers to enter normal operation */ |
@@ -189,7 +176,6 @@ int nand_open(struct nand_drv* drv) | |||
189 | return NAND_ERR_UNKNOWN_CHIP; | 176 | return NAND_ERR_UNKNOWN_CHIP; |
190 | 177 | ||
191 | setup_chip_data(drv); | 178 | setup_chip_data(drv); |
192 | setup_chip_commands(drv); | ||
193 | 179 | ||
194 | /* Set new SFC parameters */ | 180 | /* Set new SFC parameters */ |
195 | sfc_set_dev_conf(drv->chip->dev_conf); | 181 | sfc_set_dev_conf(drv->chip->dev_conf); |
@@ -234,7 +220,7 @@ static uint8_t nand_wait_busy(struct nand_drv* drv) | |||
234 | int nand_block_erase(struct nand_drv* drv, nand_block_t block) | 220 | int nand_block_erase(struct nand_drv* drv, nand_block_t block) |
235 | { | 221 | { |
236 | sfc_exec(NANDCMD_WR_EN, 0, NULL, 0); | 222 | sfc_exec(NANDCMD_WR_EN, 0, NULL, 0); |
237 | sfc_exec(drv->cmd_block_erase, block, NULL, 0); | 223 | sfc_exec(drv->chip->cmd_block_erase, block, NULL, 0); |
238 | 224 | ||
239 | uint8_t status = nand_wait_busy(drv); | 225 | uint8_t status = nand_wait_busy(drv); |
240 | if(status & FREG_STATUS_EFAIL) | 226 | if(status & FREG_STATUS_EFAIL) |
@@ -246,8 +232,9 @@ int nand_block_erase(struct nand_drv* drv, nand_block_t block) | |||
246 | int nand_page_program(struct nand_drv* drv, nand_page_t page, const void* buffer) | 232 | int nand_page_program(struct nand_drv* drv, nand_page_t page, const void* buffer) |
247 | { | 233 | { |
248 | sfc_exec(NANDCMD_WR_EN, 0, NULL, 0); | 234 | sfc_exec(NANDCMD_WR_EN, 0, NULL, 0); |
249 | sfc_exec(drv->cmd_program_load, 0, (void*)buffer, drv->fpage_size|SFC_WRITE); | 235 | sfc_exec(drv->chip->cmd_program_load, |
250 | sfc_exec(drv->cmd_program_execute, page, NULL, 0); | 236 | 0, (void*)buffer, drv->fpage_size|SFC_WRITE); |
237 | sfc_exec(drv->chip->cmd_program_execute, page, NULL, 0); | ||
251 | 238 | ||
252 | uint8_t status = nand_wait_busy(drv); | 239 | uint8_t status = nand_wait_busy(drv); |
253 | if(status & FREG_STATUS_PFAIL) | 240 | if(status & FREG_STATUS_PFAIL) |
@@ -258,9 +245,9 @@ int nand_page_program(struct nand_drv* drv, nand_page_t page, const void* buffer | |||
258 | 245 | ||
259 | int nand_page_read(struct nand_drv* drv, nand_page_t page, void* buffer) | 246 | int nand_page_read(struct nand_drv* drv, nand_page_t page, void* buffer) |
260 | { | 247 | { |
261 | sfc_exec(drv->cmd_page_read, page, NULL, 0); | 248 | sfc_exec(drv->chip->cmd_page_read, page, NULL, 0); |
262 | nand_wait_busy(drv); | 249 | nand_wait_busy(drv); |
263 | sfc_exec(drv->cmd_read_cache, 0, buffer, drv->fpage_size|SFC_READ); | 250 | sfc_exec(drv->chip->cmd_read_cache, 0, buffer, drv->fpage_size|SFC_READ); |
264 | 251 | ||
265 | if(drv->chip->flags & NAND_CHIPFLAG_ON_DIE_ECC) { | 252 | if(drv->chip->flags & NAND_CHIPFLAG_ON_DIE_ECC) { |
266 | uint8_t status = nand_get_reg(drv, FREG_STATUS); | 253 | uint8_t status = nand_get_reg(drv, FREG_STATUS); |