diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/nand-x1000.c')
| -rw-r--r-- | firmware/target/mips/ingenic_x1000/nand-x1000.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c index 1770324fb3..fbac824789 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.c +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c | |||
| @@ -200,11 +200,8 @@ static int nand_rdwr(bool write, uint32_t addr, uint32_t size, uint8_t* buf) | |||
| 200 | return NAND_SUCCESS; | 200 | return NAND_SUCCESS; |
| 201 | if(write && !nand_drv.write_enabled) | 201 | if(write && !nand_drv.write_enabled) |
| 202 | return NAND_ERR_WRITE_PROTECT; | 202 | return NAND_ERR_WRITE_PROTECT; |
| 203 | /* FIXME: re-enable this check after merging new SPL+bootloader. | 203 | if((uint32_t)buf & (CACHEALIGN_SIZE - 1)) |
| 204 | * It's only necessary for DMA, which is currently not used, but it's a | 204 | return NAND_ERR_UNALIGNED; |
| 205 | * good practice anyway. Disable for now due to SPL complications. */ | ||
| 206 | /*if((uint32_t)buf & (CACHEALIGN_SIZE - 1)) | ||
| 207 | return NAND_ERR_UNALIGNED;*/ | ||
| 208 | 205 | ||
| 209 | addr >>= nand_drv.chip_data->log2_page_size; | 206 | addr >>= nand_drv.chip_data->log2_page_size; |
| 210 | size >>= nand_drv.chip_data->log2_page_size; | 207 | size >>= nand_drv.chip_data->log2_page_size; |