3 files changed, 201 insertions, 11 deletions

diff --git a/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c b/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c
index df97aba0c8..6968a19a1c 100644
--- a/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c
+++ b/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c
@@ -104,6 +104,30 @@ void audiohw_postinit(void)
         * for 24-bit data... */
         // es9018k2m_write_reg(ES9018K2M_REG1_INPUT_CONFIG, 0b01001100); // 24-bit data
 
+       /* Datasheet: Sets the number os FSR edges that must occur before    *
+        * the DPLL and ASRC can lock on to the the incoming Signal.         *
+        * When Samplerates >= 96khz could be used, STOP_DIV should be set   *
+        * to 0 (= 16384 FSR Edges).                                         *
+        *   Reg #10 [3:0] (0x05 default, 2730 FSR Edges)                    */
+        es9018k2m_write_reg(ES9018K2M_REG10_MASTER_MODE_CTRL, 0x00);
+
+       /* Datasheet: The ES90x8Q2M/K2M contains a Jitter Eliminator block,   *
+        * which employs the use of a digital phase locked loop (DPLL) to     *
+        * lock to the incoming audio clock rate. When in I2S or SPDIF mode,  *
+        * the DPLL will lock to the frame clock (1 x fs). However, when in   *
+        * DSD mode, the DPLL has no frame clock information, and must in-    *
+        * stead lock to the bit clock rate (BCK). For this reason, there are *
+        * two bandwidth settings for the DPLL.                               *
+           Reg #12 [7:4] (0x05 default) bandwidth for I2S / SPDIF mode.
+           Reg #12 [3:0] (0x0A default) bandwidth for DSD mode.
+        * The DPLL bandwidth sets how quickly the DPLL can adjust its intern *
+        * representation of the audio clock. The higher the jitter or        *
+        * frequency drift on the audio clock, the higher the bandwidth must  *
+        * be so that the DPLL can react.                                     *
+        * ! If the bandwidth is “too low”, the DPLL will loose lock and you  *
+        * ! will hear random dropouts. (Fixed my SurfansF20 v3.2 dropouts)   */
+        es9018k2m_write_reg(ES9018K2M_REG12_DPLL_SETTINGS, 0xda);
+
     } else { /* Default to SWVOL for PCM5102A DAC */
         logf("Default to SWVOL: ret=%d", ret);
     }
@@ -139,17 +163,19 @@ void audiohw_set_volume(int vol_l, int vol_r)
     r = vol_r;
 
 #if (defined(HAVE_HEADPHONE_DETECTION) && defined(HAVE_LINEOUT_DETECTION))
-    /* make sure headphones aren't present - don't want to
-     * blow out our eardrums cranking it to full */
-    if (lineout_inserted() && !headphones_inserted())
+    /* Due to the hardware's detection method, make the Line-Out
+     * the default. The LO can only be detected if it is active
+     * (assuming a high-impedance device is attached). HP takes priority
+     * if both are present. */
+    if (headphones_inserted())
     {
-        eros_qn_switch_output(1);
-
-        l = r = eros_qn_get_volume_limit();
+        eros_qn_switch_output(0);
     }
     else
     {
-        eros_qn_switch_output(0);
+        eros_qn_switch_output(1);
+
+        l = r = eros_qn_get_volume_limit();
     }
 #endif
 
diff --git a/firmware/target/mips/ingenic_x1000/erosqnative/button-erosqnative.c b/firmware/target/mips/ingenic_x1000/erosqnative/button-erosqnative.c
index 0d2207af2a..707dc372a8 100644
--- a/firmware/target/mips/ingenic_x1000/erosqnative/button-erosqnative.c
+++ b/firmware/target/mips/ingenic_x1000/erosqnative/button-erosqnative.c
@@ -75,12 +75,26 @@ volatile signed int enc_position = 0;
 /* Value of headphone detect register */
 static uint8_t hp_detect_reg = 0x00;
 static uint8_t hp_detect_reg_old = 0x00;
+static uint8_t hp_detect_debounce1 = 0x00;
+static uint8_t hp_detect_debounce2 = 0x00;
+static uint8_t debounce_count = 0;
 
 /* Interval to poll the register */
-#define HPD_POLL_TIME (HZ/2)
+#define HPD_POLL_TIME (HZ/4)
 
 static int hp_detect_tmo_cb(struct timeout* tmo)
 {
+    if (hp_detect_debounce1 == hp_detect_debounce2){
+        if (debounce_count >= 2){
+            debounce_count = 2;
+        } else {
+            debounce_count = debounce_count + 1;
+        }
+    } else {
+        debounce_count = 0;
+        hp_detect_debounce2 = hp_detect_debounce1;
+    }
+
     i2c_descriptor* d = (i2c_descriptor*)tmo->data;
     i2c_async_queue(AXP_PMU_BUS, TIMEOUT_NOBLOCK, I2C_Q_ADD, 0, d);
     return HPD_POLL_TIME;
@@ -96,7 +110,7 @@ static void hp_detect_init(void)
         .tran_mode = I2C_READ,
         .buffer[0] = (void*)&gpio_reg,
         .count[0] = 1,
-        .buffer[1] = &hp_detect_reg,
+        .buffer[1] = &hp_detect_debounce1,
         .count[1] = 1,
         .callback = NULL,
         .arg = 0,
@@ -113,6 +127,8 @@ static void hp_detect_init(void)
     if(r >= 0)
     {
         hp_detect_reg = r;
+        hp_detect_debounce1 = r;
+        hp_detect_debounce2 = r;
         hp_detect_reg_old = hp_detect_reg;
     }
 
@@ -122,6 +138,9 @@ static void hp_detect_init(void)
 
 bool headphones_inserted(void)
 {
+    if (debounce_count > 1){
+        hp_detect_reg = hp_detect_debounce2;
+    }
     /* if the status has changed, set the output volume accordingly */
     if ((hp_detect_reg & 0x30) != (hp_detect_reg_old & 0x30))
     {
@@ -135,6 +154,9 @@ bool headphones_inserted(void)
 
 bool lineout_inserted(void)
 {
+    if (debounce_count > 1){
+        hp_detect_reg = hp_detect_debounce2;
+    }
     /* if the status has changed, set the output volume accordingly */
     if ((hp_detect_reg & 0x30) != (hp_detect_reg_old & 0x30))
     {
diff --git a/firmware/target/mips/ingenic_x1000/erosqnative/lcd-erosqnative.c b/firmware/target/mips/ingenic_x1000/erosqnative/lcd-erosqnative.c
index 0d43a3f010..bcc30a71bd 100644
--- a/firmware/target/mips/ingenic_x1000/erosqnative/lcd-erosqnative.c
+++ b/firmware/target/mips/ingenic_x1000/erosqnative/lcd-erosqnative.c
@@ -25,11 +25,138 @@
 #include "lcd-x1000.h"
 #include "gpio-x1000.h"
 #include "system.h"
+#include "devicedata.h"
 
 /* for reference on these command/data hex values, see the mipi dcs lcd spec.  *
  * Not everything here is there, but all the standard stuff is.                */
 
-static const uint32_t erosqnative_lcd_cmd_enable[] = {
+/* New Display Eroq 2.1 / Hifiwalker 1.7+ / Surfans v3.2, unknown Controller  *
+ * (partially GC9A01 register compatible)                                     *
+ *   https://espruino.microcosm.app/api/v1/files/ \                           *
+ *   9dc1b976d621a2ab3854312cce862c4a9a50dc1b.html#GC9A01 ,                   *
+ *   https://www.buydisplay.com/download/ic/GC9A01A.pdf ,                     *
+ *   https://lcddisplay.co/wp-content/uploads/2023/02/GC9A01.pdf              *
+ * Init sequence From 'EROS Q （c口）_V2.1_20231209固件.zip'                  *
+ * update.upt/.iso -> In 'uboot.bin' at 0x52da0-0x5305f                       *
+ *  http://www.eroshifi.com/download/firmware/122.html                        */
+static const uint32_t erosqnative_lcd_cmd_enable_v3[] = {
+
+    /* Unlock EXTC? */
+    LCD_INSTR_CMD,      0xfe, // Inter Register Enable1
+    LCD_INSTR_CMD,      0xef, // Inter Register Enable2
+
+    LCD_INSTR_CMD,      0x36, // Memory Access Control
+/* Bit7 1:vertical flip   0:no vertical flip
+   Bit6 1:horizontal flip 0:no horizontal flip
+   Bit3 1:BGR 0:RGB */
+    LCD_INSTR_DAT,      0x90,
+    /* Pixel Format Set */
+    LCD_INSTR_CMD,      0x3a,
+    LCD_INSTR_DAT,      0x55, /* Rockbox uses 16pp, OF specified 18 bpp */
+
+    LCD_INSTR_CMD,      0x84, // ?? (undocumented)
+    LCD_INSTR_DAT,      0x04,
+    LCD_INSTR_CMD,      0x86, // ??
+    LCD_INSTR_DAT,      0xfb,
+    LCD_INSTR_CMD,      0x87, // ??
+    LCD_INSTR_DAT,      0x79,
+    LCD_INSTR_CMD,      0x89, // ??
+    LCD_INSTR_DAT,      0x0b,
+    LCD_INSTR_CMD,      0x8a, // ??
+    LCD_INSTR_DAT,      0x20,
+    LCD_INSTR_CMD,      0x8b, // ??
+    LCD_INSTR_DAT,      0x80,
+    LCD_INSTR_CMD,      0x8d, // ??
+    LCD_INSTR_DAT,      0x3b,
+    LCD_INSTR_CMD,      0x8e, // ??
+    LCD_INSTR_DAT,      0xcf,
+
+    LCD_INSTR_CMD,      0xec, // Charge Pump Frequent Control
+    LCD_INSTR_DAT,      0x33,
+    LCD_INSTR_DAT,      0x02,
+    LCD_INSTR_DAT,      0x4c,
+
+    LCD_INSTR_CMD,      0x98, // ?? (undocumented)
+    LCD_INSTR_DAT,      0x3e,
+    LCD_INSTR_CMD,      0x9c, // ??
+    LCD_INSTR_DAT,      0x4b,
+    LCD_INSTR_CMD,      0x99, // ??
+    LCD_INSTR_DAT,      0x3e,
+    LCD_INSTR_CMD,      0x9d, // ??
+    LCD_INSTR_DAT,      0x4b,
+    LCD_INSTR_CMD,      0x9b, // ??
+    LCD_INSTR_DAT,      0x55,
+
+    LCD_INSTR_CMD,      0xe8, // Frame Rate
+    LCD_INSTR_DAT,      0x11,
+    LCD_INSTR_DAT,      0x00,
+
+    LCD_INSTR_CMD,      0xff, // ?? (Adafruit & Co lib.  C:0xFF, D:0x60, D:0x01, D:0x04)
+    LCD_INSTR_DAT,      0x62, // LCD_INSTR_DAT, 0x01, LCD_INSTR_DAT, 0x04,
+    LCD_INSTR_CMD,      0xc3, // Vreg1a voltage Control
+    LCD_INSTR_DAT,      0x20,
+    LCD_INSTR_CMD,      0xc4, // Vreg1b voltage Control
+    LCD_INSTR_DAT,      0x03,
+    LCD_INSTR_CMD,      0xc9, // Vreg2a voltage Control
+    LCD_INSTR_DAT,      0x2a,
+
+    LCD_INSTR_CMD,      0xf0, // SET_GAMMA1
+    LCD_INSTR_DAT,      0x4a,
+    LCD_INSTR_DAT,      0x10,
+    LCD_INSTR_DAT,      0x0a,
+    LCD_INSTR_DAT,      0x0a,
+    LCD_INSTR_DAT,      0x26,
+    LCD_INSTR_DAT,      0x39,
+
+    LCD_INSTR_CMD,      0xf2, // SET_GAMMA3
+    LCD_INSTR_DAT,      0x4a,
+    LCD_INSTR_DAT,      0x10,
+    LCD_INSTR_DAT,      0x0a,
+    LCD_INSTR_DAT,      0x0a,
+    LCD_INSTR_DAT,      0x26,
+    LCD_INSTR_DAT,      0x39,
+
+    LCD_INSTR_CMD,      0xf1, // SET_GAMMA2
+    LCD_INSTR_DAT,      0x50,
+    LCD_INSTR_DAT,      0x8f,
+    LCD_INSTR_DAT,      0xaf,
+    LCD_INSTR_DAT,      0x3b,
+    LCD_INSTR_DAT,      0x3f,
+    LCD_INSTR_DAT,      0x7f,
+
+    LCD_INSTR_CMD,      0xf3, // SET_GAMMA4
+    LCD_INSTR_DAT,      0x50,
+    LCD_INSTR_DAT,      0x8f,
+    LCD_INSTR_DAT,      0xaf,
+    LCD_INSTR_DAT,      0x3b,
+    LCD_INSTR_DAT,      0x3f,
+    LCD_INSTR_DAT,      0x7f,
+
+    LCD_INSTR_CMD,      0xba, // TE Control
+    LCD_INSTR_DAT,      0x0a,
+
+#ifdef BOOTLOADER
+    LCD_INSTR_CMD,      0x35, // Tearing Effect Line ON
+    LCD_INSTR_DAT,      0x00,
+#endif
+
+    LCD_INSTR_CMD,      0x21, /* Invert */
+
+    /* Lock EXTC? */
+    LCD_INSTR_CMD,      0xfe, // Inter Register Enable1
+    LCD_INSTR_CMD,      0xee,
+
+    /* Exit Sleep */
+    LCD_INSTR_CMD,      0x11,
+    LCD_INSTR_UDELAY,   120000,
+    /* Display On */
+    LCD_INSTR_CMD,      0x29,
+    LCD_INSTR_UDELAY,   20000,
+    LCD_INSTR_END,
+};
+
+/* Original Display / Hifiwalker -1.5 / Surfans -2.7 */
+static const uint32_t erosqnative_lcd_cmd_enable_v1[] = {
     /* Set EXTC? */
     LCD_INSTR_CMD,      0xc8,
     LCD_INSTR_DAT,      0xff,
@@ -179,7 +306,22 @@ void lcd_tgt_enable(bool enable)
         mdelay(5);
         gpio_set_level(GPIO_LCD_CE, 0);
 
-        lcd_exec_commands(&erosqnative_lcd_cmd_enable[0]);
+#ifdef BOOTLOADER
+# if EROSQN_VER == 3
+        lcd_exec_commands(&erosqnative_lcd_cmd_enable_v3[0]);
+# else
+        lcd_exec_commands(&erosqnative_lcd_cmd_enable_v1[0]);
+# endif
+#else
+        if (device_data.lcd_version == 3)
+        {
+            lcd_exec_commands(&erosqnative_lcd_cmd_enable_v3[0]);
+        }
+        else
+        {
+            lcd_exec_commands(&erosqnative_lcd_cmd_enable_v1[0]);
+        }
+#endif
     } else {
         /* doesn't flash white if we don't do anything... */
 #if 0