diff options
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4740.c | 25 |
1 files changed, 15 insertions, 10 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c index 291716a309..d676d20be6 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c | |||
@@ -121,7 +121,6 @@ void system_enable_irq(unsigned int irq) | |||
121 | static void dis_irq(unsigned int irq) | 121 | static void dis_irq(unsigned int irq) |
122 | { | 122 | { |
123 | register unsigned int t; | 123 | register unsigned int t; |
124 | |||
125 | if ((irq >= IRQ_GPIO_0) && (irq <= IRQ_GPIO_0 + NUM_GPIO)) | 124 | if ((irq >= IRQ_GPIO_0) && (irq <= IRQ_GPIO_0 + NUM_GPIO)) |
126 | { | 125 | { |
127 | __gpio_mask_irq(irq - IRQ_GPIO_0); | 126 | __gpio_mask_irq(irq - IRQ_GPIO_0); |
@@ -161,14 +160,20 @@ static int get_irq_number(void) | |||
161 | 160 | ||
162 | ipl |= REG_INTC_IPR; | 161 | ipl |= REG_INTC_IPR; |
163 | 162 | ||
164 | if (ipl == 0) | 163 | if (UNLIKELY(ipl == 0)) |
165 | return -1; | 164 | return -1; |
166 | 165 | ||
167 | for (irq = 31; irq >= 0; irq--) | 166 | __asm__ __volatile__("negu $8, %0 \n" |
168 | if (ipl & (1 << irq)) | 167 | "and $8, %0, $8 \n" |
169 | break; | 168 | "clz %0, %1 \n" |
169 | "li $8, 31 \n" | ||
170 | "subu %0, $8, %0 \n" | ||
171 | : "=r" (irq) | ||
172 | : "r" (ipl) | ||
173 | : "t0" | ||
174 | ); | ||
170 | 175 | ||
171 | if (irq < 0) | 176 | if (UNLIKELY(irq < 0)) |
172 | return -1; | 177 | return -1; |
173 | 178 | ||
174 | ipl &= ~(1 << irq); | 179 | ipl &= ~(1 << irq); |
@@ -197,7 +202,7 @@ static int get_irq_number(void) | |||
197 | 202 | ||
198 | void intr_handler(void) | 203 | void intr_handler(void) |
199 | { | 204 | { |
200 | int irq = get_irq_number(); | 205 | register int irq = get_irq_number(); |
201 | if(UNLIKELY(irq < 0)) | 206 | if(UNLIKELY(irq < 0)) |
202 | return; | 207 | return; |
203 | 208 | ||
@@ -313,8 +318,8 @@ static void pll_init(void) | |||
313 | 318 | ||
314 | cfcr = CPM_CPCCR_CLKOEN | | 319 | cfcr = CPM_CPCCR_CLKOEN | |
315 | CPM_CPCCR_PCS | | 320 | CPM_CPCCR_PCS | |
316 | (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | | 321 | (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | |
317 | (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | | 322 | (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | |
318 | (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) | | 323 | (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) | |
319 | (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) | | 324 | (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) | |
320 | (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT) | | 325 | (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT) | |
@@ -327,7 +332,7 @@ static void pll_init(void) | |||
327 | 332 | ||
328 | nf = CPU_FREQ * 2 / CFG_EXTAL; | 333 | nf = CPU_FREQ * 2 / CFG_EXTAL; |
329 | plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ | 334 | plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ |
330 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ | 335 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ |
331 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ | 336 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ |
332 | (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ | 337 | (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ |
333 | CPM_CPPCR_PLLEN; /* enable PLL */ | 338 | CPM_CPPCR_PLLEN; /* enable PLL */ |