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Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c10
-rw-r--r--firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c12
-rw-r--r--firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c8
-rw-r--r--firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c8
-rw-r--r--firmware/target/mips/ingenic_jz47xx/usb-jz4740.c8
5 files changed, 23 insertions, 23 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
index 22c1dc56e1..b7b239e3b9 100644
--- a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
@@ -117,7 +117,7 @@ static struct nand_param internal_param;
117static struct mutex nand_mtx; 117static struct mutex nand_mtx;
118#ifdef USE_DMA 118#ifdef USE_DMA
119static struct mutex nand_dma_mtx; 119static struct mutex nand_dma_mtx;
120static struct wakeup nand_wkup; 120static struct semaphore nand_dma_complete;
121#endif 121#endif
122static unsigned char temp_page[4096]; /* Max page size */ 122static unsigned char temp_page[4096]; /* Max page size */
123 123
@@ -170,7 +170,7 @@ static void jz_nand_write_dma(void *source, unsigned int len, int bw)
170 yield(); 170 yield();
171#else 171#else
172 REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */ 172 REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */
173 wakeup_wait(&nand_wkup, TIMEOUT_BLOCK); 173 semaphore_wait(&nand_dma_complete, TIMEOUT_BLOCK);
174#endif 174#endif
175 175
176 REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ 176 REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
@@ -202,7 +202,7 @@ static void jz_nand_read_dma(void *target, unsigned int len, int bw)
202 yield(); 202 yield();
203#else 203#else
204 REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */ 204 REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */
205 wakeup_wait(&nand_wkup, TIMEOUT_BLOCK); 205 semaphore_wait(&nand_dma_complete, TIMEOUT_BLOCK);
206#endif 206#endif
207 207
208 //REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ 208 //REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
@@ -226,7 +226,7 @@ void DMA_CALLBACK(DMA_NAND_CHANNEL)(void)
226 if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_TT) 226 if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_TT)
227 REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_TT; 227 REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_TT;
228 228
229 wakeup_signal(&nand_wkup); 229 semaphore_release(&nand_dma_complete);
230} 230}
231#endif /* USE_DMA */ 231#endif /* USE_DMA */
232 232
@@ -603,7 +603,7 @@ int nand_init(void)
603 mutex_init(&nand_mtx); 603 mutex_init(&nand_mtx);
604#ifdef USE_DMA 604#ifdef USE_DMA
605 mutex_init(&nand_dma_mtx); 605 mutex_init(&nand_dma_mtx);
606 wakeup_init(&nand_wkup); 606 semaphore_init(&nand_dma_complete, 1, 0);
607 system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL)); 607 system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL));
608#endif 608#endif
609 609
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
index efca66445a..846b9095f1 100644
--- a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
@@ -47,7 +47,7 @@ static long sd_stack[(DEFAULT_STACK_SIZE*2 + 0x1c0)/sizeof(long)];
47static const char sd_thread_name[] = "ata/sd"; 47static const char sd_thread_name[] = "ata/sd";
48static struct event_queue sd_queue; 48static struct event_queue sd_queue;
49static struct mutex sd_mtx; 49static struct mutex sd_mtx;
50static struct wakeup sd_wakeup; 50static struct semaphore sd_wakeup;
51static void sd_thread(void) NORETURN_ATTR; 51static void sd_thread(void) NORETURN_ATTR;
52 52
53static int use_4bit; 53static int use_4bit;
@@ -831,7 +831,7 @@ static int jz_sd_exec_cmd(struct sd_request *request)
831 831
832 /* Wait for command completion */ 832 /* Wait for command completion */
833 //__intc_unmask_irq(IRQ_MSC); 833 //__intc_unmask_irq(IRQ_MSC);
834 //wakeup_wait(&sd_wakeup, 100); 834 //semaphore_wait(&sd_wakeup, 100);
835 while (timeout-- && !(REG_MSC_STAT & MSC_STAT_END_CMD_RES)); 835 while (timeout-- && !(REG_MSC_STAT & MSC_STAT_END_CMD_RES));
836 836
837 837
@@ -881,7 +881,7 @@ static int jz_sd_exec_cmd(struct sd_request *request)
881#endif 881#endif
882 } 882 }
883 //__intc_unmask_irq(IRQ_MSC); 883 //__intc_unmask_irq(IRQ_MSC);
884 //wakeup_wait(&sd_wakeup, 100); 884 //semaphore_wait(&sd_wakeup, 100);
885 /* Wait for Data Done */ 885 /* Wait for Data Done */
886 while (!(REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE)); 886 while (!(REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE));
887 REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE; /* clear status */ 887 REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE; /* clear status */
@@ -891,7 +891,7 @@ static int jz_sd_exec_cmd(struct sd_request *request)
891 if (events & SD_EVENT_PROG_DONE) 891 if (events & SD_EVENT_PROG_DONE)
892 { 892 {
893 //__intc_unmask_irq(IRQ_MSC); 893 //__intc_unmask_irq(IRQ_MSC);
894 //wakeup_wait(&sd_wakeup, 100); 894 //semaphore_wait(&sd_wakeup, 100);
895 while (!(REG_MSC_IREG & MSC_IREG_PRG_DONE)); 895 while (!(REG_MSC_IREG & MSC_IREG_PRG_DONE));
896 REG_MSC_IREG = MSC_IREG_PRG_DONE; /* clear status */ 896 REG_MSC_IREG = MSC_IREG_PRG_DONE; /* clear status */
897 } 897 }
@@ -945,7 +945,7 @@ static void jz_sd_rx_handler(unsigned int arg)
945/* MSC interrupt handler */ 945/* MSC interrupt handler */
946void MSC(void) 946void MSC(void)
947{ 947{
948 //wakeup_signal(&sd_wakeup); 948 //semaphore_release(&sd_wakeup);
949 logf("MSC interrupt"); 949 logf("MSC interrupt");
950} 950}
951 951
@@ -1228,7 +1228,7 @@ int sd_init(void)
1228 static bool inited = false; 1228 static bool inited = false;
1229 if(!inited) 1229 if(!inited)
1230 { 1230 {
1231 wakeup_init(&sd_wakeup); 1231 semaphore_init(&sd_wakeup, 1, 0);
1232 mutex_init(&sd_mtx); 1232 mutex_init(&sd_mtx);
1233 queue_init(&sd_queue, true); 1233 queue_init(&sd_queue, true);
1234 create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0, 1234 create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
index ef45317c3f..e74e227e47 100644
--- a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
@@ -34,7 +34,7 @@
34 34
35static volatile bool lcd_is_on = false; 35static volatile bool lcd_is_on = false;
36static struct mutex lcd_mtx; 36static struct mutex lcd_mtx;
37static struct wakeup lcd_wkup; 37static struct semaphore lcd_wkup;
38static int lcd_count = 0; 38static int lcd_count = 0;
39 39
40void lcd_clock_enable(void) 40void lcd_clock_enable(void)
@@ -56,7 +56,7 @@ void lcd_init_device(void)
56 56
57 lcd_is_on = true; 57 lcd_is_on = true;
58 mutex_init(&lcd_mtx); 58 mutex_init(&lcd_mtx);
59 wakeup_init(&lcd_wkup); 59 semaphore_init(&lcd_wkup, 1, 0);
60 system_enable_irq(DMA_IRQ(DMA_LCD_CHANNEL)); 60 system_enable_irq(DMA_IRQ(DMA_LCD_CHANNEL));
61} 61}
62 62
@@ -118,7 +118,7 @@ void lcd_update_rect(int x, int y, int width, int height)
118 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ 118 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */
119 REG_DMAC_DCMD(DMA_LCD_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */ 119 REG_DMAC_DCMD(DMA_LCD_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */
120 120
121 wakeup_wait(&lcd_wkup, TIMEOUT_BLOCK); /* Sleeping in lcd_update() should be safe */ 121 semaphore_wait(&lcd_wkup, TIMEOUT_BLOCK); /* Sleeping in lcd_update() should be safe */
122 122
123 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ 123 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
124 dma_disable(); 124 dma_disable();
@@ -145,7 +145,7 @@ void DMA_CALLBACK(DMA_LCD_CHANNEL)(void)
145 if (REG_DMAC_DCCSR(DMA_LCD_CHANNEL) & DMAC_DCCSR_TT) 145 if (REG_DMAC_DCCSR(DMA_LCD_CHANNEL) & DMAC_DCCSR_TT)
146 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_TT; 146 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_TT;
147 147
148 wakeup_signal(&lcd_wkup); 148 semaphore_release(&lcd_wkup);
149} 149}
150 150
151/* Update the display. 151/* Update the display.
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c
index 92cf0d7552..99d73fa3c7 100644
--- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c
@@ -74,7 +74,7 @@ static int datacount = 0;
74static volatile int cur_touch = 0; 74static volatile int cur_touch = 0;
75static volatile bool pen_down = false; 75static volatile bool pen_down = false;
76static struct mutex battery_mtx; 76static struct mutex battery_mtx;
77static struct wakeup battery_wkup; 77static struct semaphore battery_done;
78 78
79const unsigned short battery_level_dangerous[BATTERY_TYPES_COUNT] = 79const unsigned short battery_level_dangerous[BATTERY_TYPES_COUNT] =
80{ 80{
@@ -113,7 +113,7 @@ unsigned int battery_adc_voltage(void)
113 113
114 REG_SADC_ENA |= SADC_ENA_PBATEN; 114 REG_SADC_ENA |= SADC_ENA_PBATEN;
115 115
116 wakeup_wait(&battery_wkup, HZ/4); 116 semaphore_wait(&battery_done, HZ/4);
117 bat_val = REG_SADC_BATDAT; 117 bat_val = REG_SADC_BATDAT;
118 118
119 logf("%d %d", bat_val, (bat_val * BATTERY_SCALE_FACTOR) / 4096); 119 logf("%d %d", bat_val, (bat_val * BATTERY_SCALE_FACTOR) / 4096);
@@ -268,7 +268,7 @@ void SADC(void)
268 if(state & SADC_CTRL_PBATRDYM) 268 if(state & SADC_CTRL_PBATRDYM)
269 { 269 {
270 /* Battery AD IRQ */ 270 /* Battery AD IRQ */
271 wakeup_signal(&battery_wkup); 271 semaphore_release(&battery_done);
272 } 272 }
273} 273}
274 274
@@ -290,7 +290,7 @@ void adc_init(void)
290 REG_SADC_ENA = SADC_ENA_TSEN; 290 REG_SADC_ENA = SADC_ENA_TSEN;
291 291
292 mutex_init(&battery_mtx); 292 mutex_init(&battery_mtx);
293 wakeup_init(&battery_wkup); 293 semaphore_init(&battery_done, 1, 0);
294} 294}
295 295
296void adc_close(void) 296void adc_close(void)
diff --git a/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c b/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c
index f12f1bed82..a615d3d4da 100644
--- a/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c
@@ -69,7 +69,7 @@ struct usb_endpoint
69 unsigned short fifo_size; 69 unsigned short fifo_size;
70 70
71 bool wait; 71 bool wait;
72 struct wakeup wakeup; 72 struct semaphore complete;
73}; 73};
74 74
75static unsigned char ep0_rx_buf[64]; 75static unsigned char ep0_rx_buf[64];
@@ -171,7 +171,7 @@ static inline void ep_transfer_completed(struct usb_endpoint* ep)
171 ep->buf = NULL; 171 ep->buf = NULL;
172 ep->busy = false; 172 ep->busy = false;
173 if(ep->wait) 173 if(ep->wait)
174 wakeup_signal(&ep->wakeup); 174 semaphore_release(&ep->complete);
175} 175}
176 176
177static void EP0_send(void) 177static void EP0_send(void)
@@ -598,7 +598,7 @@ void usb_init_device(void)
598 system_enable_irq(IRQ_UDC); 598 system_enable_irq(IRQ_UDC);
599 599
600 for(i=0; i<TOTAL_EP(); i++) 600 for(i=0; i<TOTAL_EP(); i++)
601 wakeup_init(&endpoints[i].wakeup); 601 semaphore_init(&endpoints[i].complete, 1, 0);
602} 602}
603 603
604#ifdef USB_GPIO_IRQ 604#ifdef USB_GPIO_IRQ
@@ -715,7 +715,7 @@ static void usb_drv_send_internal(struct usb_endpoint* ep, void* ptr, int length
715 715
716 if(blocking) 716 if(blocking)
717 { 717 {
718 wakeup_wait(&ep->wakeup, TIMEOUT_BLOCK); 718 semaphore_wait(&ep->complete, TIMEOUT_BLOCK);
719 ep->wait = false; 719 ep->wait = false;
720 } 720 }
721} 721}