diff options
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-jz4740.c')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4740.c | 101 |
1 files changed, 1 insertions, 100 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c index 033b42214b..9c7f83530f 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include "jz4740.h" | 23 | #include "jz4740.h" |
24 | #include "mips.h" | 24 | #include "mips.h" |
25 | #include "mipsregs.h" | 25 | #include "mipsregs.h" |
26 | #include "mmu-mips.h" | ||
26 | #include "panic.h" | 27 | #include "panic.h" |
27 | #include "system.h" | 28 | #include "system.h" |
28 | #include "string.h" | 29 | #include "string.h" |
@@ -524,106 +525,6 @@ void dma_cache_wback_inv(unsigned long addr, unsigned long size) | |||
524 | } | 525 | } |
525 | } | 526 | } |
526 | 527 | ||
527 | #define BARRIER \ | ||
528 | __asm__ __volatile__( \ | ||
529 | " .set noreorder \n" \ | ||
530 | " nop \n" \ | ||
531 | " nop \n" \ | ||
532 | " nop \n" \ | ||
533 | " nop \n" \ | ||
534 | " nop \n" \ | ||
535 | " nop \n" \ | ||
536 | " .set reorder \n"); | ||
537 | |||
538 | #define DEFAULT_PAGE_SHIFT PL_4K | ||
539 | #define DEFAULT_PAGE_MASK PM_4K | ||
540 | #define UNIQUE_ENTRYHI(idx, ps) (A_K0BASE + ((idx) << (ps + 1))) | ||
541 | #define ASID_MASK M_EntryHiASID | ||
542 | #define VPN2_SHIFT S_EntryHiVPN2 | ||
543 | #define PFN_SHIFT S_EntryLoPFN | ||
544 | #define PFN_MASK 0xffffff | ||
545 | static void local_flush_tlb_all(void) | ||
546 | { | ||
547 | unsigned long old_ctx; | ||
548 | int entry; | ||
549 | unsigned int old_irq = disable_irq_save(); | ||
550 | |||
551 | /* Save old context and create impossible VPN2 value */ | ||
552 | old_ctx = read_c0_entryhi(); | ||
553 | write_c0_entrylo0(0); | ||
554 | write_c0_entrylo1(0); | ||
555 | BARRIER; | ||
556 | |||
557 | /* Blast 'em all away. */ | ||
558 | for(entry = 0; entry < 32; entry++) | ||
559 | { | ||
560 | /* Make sure all entries differ. */ | ||
561 | write_c0_entryhi(UNIQUE_ENTRYHI(entry, DEFAULT_PAGE_SHIFT)); | ||
562 | write_c0_index(entry); | ||
563 | BARRIER; | ||
564 | tlb_write_indexed(); | ||
565 | } | ||
566 | BARRIER; | ||
567 | write_c0_entryhi(old_ctx); | ||
568 | |||
569 | restore_irq(old_irq); | ||
570 | } | ||
571 | |||
572 | static void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, | ||
573 | unsigned long entryhi, unsigned long pagemask) | ||
574 | { | ||
575 | unsigned long wired; | ||
576 | unsigned long old_pagemask; | ||
577 | unsigned long old_ctx; | ||
578 | unsigned int old_irq = disable_irq_save(); | ||
579 | |||
580 | old_ctx = read_c0_entryhi() & ASID_MASK; | ||
581 | old_pagemask = read_c0_pagemask(); | ||
582 | wired = read_c0_wired(); | ||
583 | write_c0_wired(wired + 1); | ||
584 | write_c0_index(wired); | ||
585 | BARRIER; | ||
586 | write_c0_pagemask(pagemask); | ||
587 | write_c0_entryhi(entryhi); | ||
588 | write_c0_entrylo0(entrylo0); | ||
589 | write_c0_entrylo1(entrylo1); | ||
590 | BARRIER; | ||
591 | tlb_write_indexed(); | ||
592 | BARRIER; | ||
593 | |||
594 | write_c0_entryhi(old_ctx); | ||
595 | BARRIER; | ||
596 | write_c0_pagemask(old_pagemask); | ||
597 | local_flush_tlb_all(); | ||
598 | restore_irq(old_irq); | ||
599 | } | ||
600 | |||
601 | static void map_address(unsigned long virtual, unsigned long physical, unsigned long length) | ||
602 | { | ||
603 | unsigned long entry0 = (physical & PFN_MASK) << PFN_SHIFT; | ||
604 | unsigned long entry1 = ((physical+length) & PFN_MASK) << PFN_SHIFT; | ||
605 | unsigned long entryhi = virtual & ~VPN2_SHIFT; | ||
606 | |||
607 | entry0 |= (M_EntryLoG | M_EntryLoV | (K_CacheAttrC << S_EntryLoC) ); | ||
608 | entry1 |= (M_EntryLoG | M_EntryLoV | (K_CacheAttrC << S_EntryLoC) ); | ||
609 | |||
610 | add_wired_entry(entry0, entry1, entryhi, DEFAULT_PAGE_MASK); | ||
611 | } | ||
612 | |||
613 | |||
614 | static void tlb_init(void) | ||
615 | { | ||
616 | write_c0_pagemask(DEFAULT_PAGE_MASK); | ||
617 | write_c0_wired(0); | ||
618 | write_c0_framemask(0); | ||
619 | |||
620 | local_flush_tlb_all(); | ||
621 | /* | ||
622 | map_address(0x80000000, 0x80000000, 0x4000); | ||
623 | map_address(0x80004000, 0x80004000, MEM * 0x100000); | ||
624 | */ | ||
625 | } | ||
626 | |||
627 | void tlb_refill_handler(void) | 528 | void tlb_refill_handler(void) |
628 | { | 529 | { |
629 | panicf("TLB refill handler at 0x%08lx! [0x%x]", read_c0_epc(), read_c0_badvaddr()); | 530 | panicf("TLB refill handler at 0x%08lx! [0x%x]", read_c0_epc(), read_c0_badvaddr()); |