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Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c47
1 files changed, 34 insertions, 13 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c b/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c
index 0343723493..5549ce4dbf 100644
--- a/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c
@@ -27,13 +27,14 @@
27#include "pcm.h" 27#include "pcm.h"
28#include "jz4740.h" 28#include "jz4740.h"
29 29
30
30/**************************************************************************** 31/****************************************************************************
31 ** Playback DMA transfer 32 ** Playback DMA transfer
32 **/ 33 **/
33 34
34void pcm_postinit(void) 35void pcm_postinit(void)
35{ 36{
36 audiohw_postinit(); /* implemented not for all codecs */ 37 audiohw_postinit();
37 pcm_apply_settings(); 38 pcm_apply_settings();
38} 39}
39 40
@@ -61,29 +62,55 @@ void pcm_set_frequency(unsigned int frequency)
61{ 62{
62 (void) frequency; 63 (void) frequency;
63 /* TODO */ 64 /* TODO */
65
66 /*
67 __i2s_set_oss_sample_size(frequency);
68 i2s_codec_set_samplerate(frequency);
69 */
64} 70}
65 71
66static void play_start_pcm(void) 72static void play_start_pcm(void)
67{ 73{
68 pcm_apply_settings(); 74 pcm_apply_settings();
69 75
70 /* TODO */ 76 __aic_enable_transmit_dma();
77 __aic_enable_replay();
78
79 REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN;
71} 80}
72 81
73static void play_stop_pcm(void) 82static void play_stop_pcm(void)
74{ 83{
75 /* TODO */ 84 REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) | DMAC_DCCSR_HLT) & ~DMAC_DCCSR_EN;
85
86 __aic_disable_transmit_dma();
87 __aic_disable_replay();
76} 88}
77 89
78void pcm_play_dma_start(const void *addr, size_t size) 90void pcm_play_dma_start(const void *addr, size_t size)
79{ 91{
80 (void)addr; 92 REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = 0;
81 (void)size; 93 REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)addr);
82 /* TODO */ 94 REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR);
95 REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) = size;
96 REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL) = DMAC_DRSR_RS_AICOUT;
97 REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = ( DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DWDH_32
98 | DMAC_DCMD_TIE);
83 99
84 play_start_pcm(); 100 play_start_pcm();
85} 101}
86 102
103void DMA_CALLBACK(DMA_AIC_TX_CHANNEL)(void)
104{
105 if( REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) & DMAC_DCCSR_TT )
106 __aic_disable_transmit_dma();
107}
108
109size_t pcm_get_bytes_waiting(void)
110{
111 return REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL);
112}
113
87void pcm_play_dma_stop(void) 114void pcm_play_dma_stop(void)
88{ 115{
89 play_stop_pcm(); 116 play_stop_pcm();
@@ -110,12 +137,6 @@ void pcm_play_dma_pause(bool pause)
110 137
111} 138}
112 139
113size_t pcm_get_bytes_waiting(void)
114{
115 /* TODO */
116 return 0;
117}
118
119#ifdef HAVE_RECORDING 140#ifdef HAVE_RECORDING
120/* TODO */ 141/* TODO */
121void pcm_rec_dma_init(void) 142void pcm_rec_dma_init(void)