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Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/codec-jz4740.c')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/codec-jz4740.c27
1 files changed, 13 insertions, 14 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c b/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c
index b91b7fae70..3a124e1356 100644
--- a/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c
@@ -27,7 +27,8 @@
27 27
28/* TODO */ 28/* TODO */
29const struct sound_settings_info audiohw_settings[] = { 29const struct sound_settings_info audiohw_settings[] = {
30 [SOUND_VOLUME] = {"dB", 0, 2, 0, 6, 0}, 30 /* HAVE_SW_VOLUME_CONTROL */
31 [SOUND_VOLUME] = {"dB", 0, 1, SW_VOLUME_MIN, 6, 0},
31 /* HAVE_SW_TONE_CONTROLS */ 32 /* HAVE_SW_TONE_CONTROLS */
32 [SOUND_BASS] = {"dB", 0, 1, -24, 24, 0}, 33 [SOUND_BASS] = {"dB", 0, 1, -24, 24, 0},
33 [SOUND_TREBLE] = {"dB", 0, 1, -24, 24, 0}, 34 [SOUND_TREBLE] = {"dB", 0, 1, -24, 24, 0},
@@ -79,7 +80,7 @@ static void i2s_codec_init(void)
79 80
80 REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); 81 REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST);
81 82
82 REG_ICDC_CDCCR2 = ( ICDC_CDCCR2_AINVOL(14) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_44) 83 REG_ICDC_CDCCR2 = ( ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_44)
83 | ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_0)); 84 | ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_0));
84 85
85 mdelay(15); 86 mdelay(15);
@@ -287,9 +288,14 @@ void audiohw_init(void)
287 288
288void audiohw_set_volume(int v) 289void audiohw_set_volume(int v)
289{ 290{
290 /* 0 <= v <= 60 */ 291 if(v >= 0)
291 unsigned int codec_volume = v / 20; 292 {
292 REG_ICDC_CDCCR2 = (REG_ICDC_CDCCR2 & ~ICDC_CDCCR2_HPVOL(0x3)) | ICDC_CDCCR2_HPVOL(codec_volume); 293 /* 0 <= v <= 60 */
294 unsigned int codec_volume = ICDC_CDCCR2_HPVOL(v / 20);
295
296 if((REG_ICDC_CDCCR2 & ICDC_CDCCR2_HPVOL(0x3)) != codec_volume)
297 REG_ICDC_CDCCR2 = (REG_ICDC_CDCCR2 & ~ICDC_CDCCR2_HPVOL(0x3)) | codec_volume;
298 }
293} 299}
294 300
295void audiohw_set_frequency(int freq) 301void audiohw_set_frequency(int freq)
@@ -329,7 +335,8 @@ void audiohw_set_frequency(int freq)
329 return; 335 return;
330 } 336 }
331 337
332 REG_ICDC_CDCCR2 = (REG_ICDC_CDCCR2 & ~ICDC_CDCCR2_SMPR(0xF)) | speed; 338 if((REG_ICDC_CDCCR2 & ICDC_CDCCR2_SMPR(0xF)) != speed)
339 REG_ICDC_CDCCR2 = (REG_ICDC_CDCCR2 & ~ICDC_CDCCR2_SMPR(0xF)) | speed;
333} 340}
334 341
335int audio_channels = 2; 342int audio_channels = 2;
@@ -356,20 +363,16 @@ void audio_input_mux(int source, unsigned flags)
356 case AUDIO_SRC_PLAYBACK: 363 case AUDIO_SRC_PLAYBACK:
357 audio_channels = 2; 364 audio_channels = 2;
358 if(source != last_source) 365 if(source != last_source)
359 {
360 REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_ELININ | ICDC_CDCCR1_EMIC | ICDC_CDCCR1_EADC | ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_HPMUTE)) 366 REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_ELININ | ICDC_CDCCR1_EMIC | ICDC_CDCCR1_EADC | ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_HPMUTE))
361 | (ICDC_CDCCR1_EDAC | ICDC_CDCCR1_SW2ON); 367 | (ICDC_CDCCR1_EDAC | ICDC_CDCCR1_SW2ON);
362 }
363 break; 368 break;
364 369
365#if INPUT_SRC_CAPS & SRC_CAP_MIC 370#if INPUT_SRC_CAPS & SRC_CAP_MIC
366 case AUDIO_SRC_MIC: /* recording only */ 371 case AUDIO_SRC_MIC: /* recording only */
367 audio_channels = 1; 372 audio_channels = 1;
368 if(source != last_source) 373 if(source != last_source)
369 {
370 REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_ELININ | ICDC_CDCCR1_EDAC | ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_HPMUTE)) 374 REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_ELININ | ICDC_CDCCR1_EDAC | ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_HPMUTE))
371 | (ICDC_CDCCR1_EADC | ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_EMIC); 375 | (ICDC_CDCCR1_EADC | ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_EMIC);
372 }
373 break; 376 break;
374#endif 377#endif
375 378
@@ -383,15 +386,11 @@ void audio_input_mux(int source, unsigned flags)
383 last_recording = recording; 386 last_recording = recording;
384 387
385 if(recording) 388 if(recording)
386 {
387 REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_EMIC | ICDC_CDCCR1_EDAC | ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_HPMUTE)) 389 REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_EMIC | ICDC_CDCCR1_EDAC | ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_HPMUTE))
388 | (ICDC_CDCCR1_EADC | ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_ELININ); 390 | (ICDC_CDCCR1_EADC | ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_ELININ);
389 }
390 else 391 else
391 {
392 REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_EMIC | ICDC_CDCCR1_EDAC | ICDC_CDCCR1_EADC | 392 REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_EMIC | ICDC_CDCCR1_EDAC | ICDC_CDCCR1_EADC |
393 ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_HPMUTE)) | (ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_ELININ); 393 ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_HPMUTE)) | (ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_ELININ);
394 }
395 break; 394 break;
396#endif 395#endif
397 } /* end switch */ 396 } /* end switch */