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Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c91
1 files changed, 36 insertions, 55 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
index d95c88c787..957db2af0e 100644
--- a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
@@ -732,80 +732,76 @@ static void jz_sd_get_response(struct sd_request *request)
732} 732}
733 733
734#ifdef SD_DMA_ENABLE 734#ifdef SD_DMA_ENABLE
735static int jz_sd_receive_data_dma(struct sd_request *req) 735static void jz_sd_receive_data_dma(struct sd_request *req)
736{ 736{
737 int ch = RX_DMA_CHANNEL;
738 unsigned int size = req->block_len * req->nob; 737 unsigned int size = req->block_len * req->nob;
738#if MMC_DMA_INTERRUPT
739 unsigned char err = 0; 739 unsigned char err = 0;
740#endif
740 741
741 /* flush dcache */ 742 /* flush dcache */
742 dma_cache_wback_inv((unsigned long) req->buffer, size); 743 //dma_cache_wback_inv((unsigned long) req->buffer, size);
743 /* setup dma channel */ 744 /* setup dma channel */
744 REG_DMAC_DSAR(ch) = PHYSADDR(MSC_RXFIFO); /* DMA source addr */ 745 REG_DMAC_DSAR(DMA_SD_RX_CHANNEL) = PHYSADDR(MSC_RXFIFO); /* DMA source addr */
745 REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long) req->buffer); /* DMA dest addr */ 746 REG_DMAC_DTAR(DMA_SD_RX_CHANNEL) = PHYSADDR((unsigned long) req->buffer); /* DMA dest addr */
746 REG_DMAC_DTCR(ch) = (size + 3) / 4; /* DMA transfer count */ 747 REG_DMAC_DTCR(DMA_SD_RX_CHANNEL) = (size + 3) / 4; /* DMA transfer count */
747 REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_MSCIN; /* DMA request type */ 748 REG_DMAC_DRSR(DMA_SD_RX_CHANNEL) = DMAC_DRSR_RS_MSCIN; /* DMA request type */
748 749
749#if SD_DMA_INTERRUPT 750#if SD_DMA_INTERRUPT
750 REG_DMAC_DCMD(ch) = 751 REG_DMAC_DCMD(DMA_SD_RX_CHANNEL) =
751 DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | 752 DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
752 DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE; 753 DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE;
753 REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; 754 REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
754 OSSemPend(sd_dma_rx_sem, 100, &err); 755 OSSemPend(sd_dma_rx_sem, 100, &err);
755#else 756#else
756 REG_DMAC_DCMD(ch) = 757 REG_DMAC_DCMD(DMA_SD_RX_CHANNEL) =
757 DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | 758 DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
758 DMAC_DCMD_DS_32BIT; 759 DMAC_DCMD_DS_32BIT;
759 REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; 760 REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
760 while (REG_DMAC_DTCR(ch)); 761
761#endif 762 //while (REG_DMAC_DTCR(DMA_SD_RX_CHANNEL));
762/* clear status and disable channel */ 763 while( !(REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) & DMAC_DCCSR_TT) );
763 REG_DMAC_DCCSR(ch) = 0;
764#if SD_DMA_INTERRUPT
765 return (err == OS_NO_ERR);
766#else
767 return 0;
768#endif 764#endif
765
766 /* clear status and disable channel */
767 REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = 0;
769} 768}
770 769
771static int jz_sd_transmit_data_dma(struct sd_request *req) 770static void jz_mmc_transmit_data_dma(struct mmc_request *req)
772{ 771{
773 int ch = TX_DMA_CHANNEL;
774 unsigned int size = req->block_len * req->nob; 772 unsigned int size = req->block_len * req->nob;
773#if SD_DMA_INTERRUPT
775 unsigned char err = 0; 774 unsigned char err = 0;
775#endif
776 776
777 /* flush dcache */ 777 /* flush dcache */
778 dma_cache_wback_inv((unsigned long) req->buffer, size); 778 //dma_cache_wback_inv((unsigned long) req->buffer, size);
779 /* setup dma channel */ 779 /* setup dma channel */
780 REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long) req->buffer); /* DMA source addr */ 780 REG_DMAC_DSAR(DMA_SD_TX_CHANNEL) = PHYSADDR((unsigned long) req->buffer); /* DMA source addr */
781 REG_DMAC_DTAR(ch) = PHYSADDR(MSC_TXFIFO); /* DMA dest addr */ 781 REG_DMAC_DTAR(DMA_SD_TX_CHANNEL) = PHYSADDR(MSC_TXFIFO); /* DMA dest addr */
782 REG_DMAC_DTCR(ch) = (size + 3) / 4; /* DMA transfer count */ 782 REG_DMAC_DTCR(DMA_SD_TX_CHANNEL) = (size + 3) / 4; /* DMA transfer count */
783 REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_MSCOUT; /* DMA request type */ 783 REG_DMAC_DRSR(DMA_SD_TX_CHANNEL) = DMAC_DRSR_RS_MSCOUT; /* DMA request type */
784 784
785#if SD_DMA_INTERRUPT 785#if SD_DMA_INTERRUPT
786 REG_DMAC_DCMD(ch) = 786 REG_DMAC_DCMD(DMA_SD_TX_CHANNEL) =
787 DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | 787 DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
788 DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE; 788 DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE;
789 REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; 789 REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
790 OSSemPend(sd_dma_tx_sem, 100, &err); 790 OSSemPend(sd_dma_tx_sem, 100, &err);
791#else 791#else
792 REG_DMAC_DCMD(ch) = 792 REG_DMAC_DCMD(DMA_SD_TX_CHANNEL) =
793 DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | 793 DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
794 DMAC_DCMD_DS_32BIT; 794 DMAC_DCMD_DS_32BIT;
795 REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; 795 REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
796 /* wait for dma completion */ 796 /* wait for dma completion */
797 while (REG_DMAC_DTCR(ch)); 797 while( !(REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) & DMAC_DCCSR_TT) );
798#endif 798#endif
799 /* clear status and disable channel */ 799 /* clear status and disable channel */
800 REG_DMAC_DCCSR(ch) = 0; 800
801#if SD_DMA_INTERRUPT 801 REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = 0;
802 return (err == OS_NO_ERR);
803#else
804 return 0;
805#endif
806} 802}
807 803
808#endif /* SD_DMA_ENABLE */ 804#else /* SD_DMA_ENABLE */
809 805
810static int jz_sd_receive_data(struct sd_request *req) 806static int jz_sd_receive_data(struct sd_request *req)
811{ 807{
@@ -830,10 +826,9 @@ static int jz_sd_receive_data(struct sd_request *req)
830 else if (stat & MSC_STAT_CRC_READ_ERROR) 826 else if (stat & MSC_STAT_CRC_READ_ERROR)
831 return SD_ERROR_CRC; 827 return SD_ERROR_CRC;
832 else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY) 828 else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY)
833 || (stat & MSC_STAT_DATA_FIFO_AFULL)) { 829 || (stat & MSC_STAT_DATA_FIFO_AFULL))
834 /* Ready to read data */ 830 /* Ready to read data */
835 break; 831 break;
836 }
837 832
838 udelay(1); 833 udelay(1);
839 } 834 }
@@ -889,10 +884,8 @@ static int jz_sd_transmit_data(struct sd_request *req)
889 MSC_STAT_CRC_WRITE_ERROR_NOSTS)) 884 MSC_STAT_CRC_WRITE_ERROR_NOSTS))
890 return SD_ERROR_CRC; 885 return SD_ERROR_CRC;
891 else if (!(stat & MSC_STAT_DATA_FIFO_FULL)) 886 else if (!(stat & MSC_STAT_DATA_FIFO_FULL))
892 {
893 /* Ready to write data */ 887 /* Ready to write data */
894 break; 888 break;
895 }
896 889
897 udelay(1); 890 udelay(1);
898 } 891 }
@@ -923,6 +916,7 @@ static int jz_sd_transmit_data(struct sd_request *req)
923 916
924 return SD_NO_ERROR; 917 return SD_NO_ERROR;
925} 918}
919#endif
926 920
927static inline unsigned int jz_sd_calc_clkrt(int is_sd, unsigned int rate) 921static inline unsigned int jz_sd_calc_clkrt(int is_sd, unsigned int rate)
928{ 922{
@@ -1726,24 +1720,11 @@ int sd_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const vo
1726 return retval; 1720 return retval;
1727} 1721}
1728 1722
1729void sd_sleep(void)
1730{
1731}
1732
1733void sd_spin(void)
1734{
1735}
1736
1737long sd_last_disk_activity(void) 1723long sd_last_disk_activity(void)
1738{ 1724{
1739 return last_disk_activity; 1725 return last_disk_activity;
1740} 1726}
1741 1727
1742void sd_spindown(int seconds)
1743{
1744 (void)seconds;
1745}
1746
1747#ifdef HAVE_HOTSWAP 1728#ifdef HAVE_HOTSWAP
1748bool sd_removable(IF_MV_NONVOID(int drive)) 1729bool sd_removable(IF_MV_NONVOID(int drive))
1749{ 1730{