diff options
Diffstat (limited to 'firmware/target/coldfire/pcm-coldfire.c')
-rw-r--r-- | firmware/target/coldfire/pcm-coldfire.c | 36 |
1 files changed, 7 insertions, 29 deletions
diff --git a/firmware/target/coldfire/pcm-coldfire.c b/firmware/target/coldfire/pcm-coldfire.c index 6b92f9cc14..0048c9990c 100644 --- a/firmware/target/coldfire/pcm-coldfire.c +++ b/firmware/target/coldfire/pcm-coldfire.c | |||
@@ -26,6 +26,9 @@ | |||
26 | #elif defined(HAVE_TLV320) | 26 | #elif defined(HAVE_TLV320) |
27 | #include "tlv320.h" | 27 | #include "tlv320.h" |
28 | #endif | 28 | #endif |
29 | #if defined(HAVE_SPDIF_IN) || defined(HAVE_SPDIF_OUT) | ||
30 | #include "spdif.h" | ||
31 | #endif | ||
29 | 32 | ||
30 | /* Avoid further #ifdef's for some codec functions */ | 33 | /* Avoid further #ifdef's for some codec functions */ |
31 | #if defined(HAVE_UDA1380) | 34 | #if defined(HAVE_UDA1380) |
@@ -69,10 +72,6 @@ static int rec_peak_left, rec_peak_right; | |||
69 | #define IIS_CONFIG IIS2CONFIG | 72 | #define IIS_CONFIG IIS2CONFIG |
70 | #define PLLCR_SET_AUDIO_BITS_DEFPARM \ | 73 | #define PLLCR_SET_AUDIO_BITS_DEFPARM \ |
71 | ((freq_ent[FPARM_CLSEL] << 28) | (3 << 22)) | 74 | ((freq_ent[FPARM_CLSEL] << 28) | (3 << 22)) |
72 | |||
73 | #ifdef HAVE_SPDIF_OUT | ||
74 | #define EBU_DEFPARM ((7 << 12) | (3 << 8) | (1 << 5) | (5 << 2)) | ||
75 | #endif | ||
76 | #endif | 75 | #endif |
77 | 76 | ||
78 | /** Sample rates **/ | 77 | /** Sample rates **/ |
@@ -229,11 +228,6 @@ void pcm_play_dma_start(const void *addr, size_t size) | |||
229 | 228 | ||
230 | pcm_playing = true; | 229 | pcm_playing = true; |
231 | 230 | ||
232 | /* Reset the audio FIFO */ | ||
233 | #ifdef HAVE_SPDIF_OUT | ||
234 | EBU1CONFIG = IIS_RESET | EBU_DEFPARM; | ||
235 | #endif | ||
236 | |||
237 | /* Set up DMA transfer */ | 231 | /* Set up DMA transfer */ |
238 | SAR0 = (unsigned long)addr; /* Source address */ | 232 | SAR0 = (unsigned long)addr; /* Source address */ |
239 | DAR0 = (unsigned long)&PDOR3; /* Destination address */ | 233 | DAR0 = (unsigned long)&PDOR3; /* Destination address */ |
@@ -242,11 +236,6 @@ void pcm_play_dma_start(const void *addr, size_t size) | |||
242 | /* Enable the FIFO and force one write to it */ | 236 | /* Enable the FIFO and force one write to it */ |
243 | pcm_apply_settings(false); | 237 | pcm_apply_settings(false); |
244 | 238 | ||
245 | /* Also send the audio to S/PDIF */ | ||
246 | #ifdef HAVE_SPDIF_OUT | ||
247 | EBU1CONFIG = EBU_DEFPARM; | ||
248 | #endif | ||
249 | |||
250 | DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | | 239 | DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | |
251 | DMA_SINC | DMA_SSIZE(3) | DMA_START; | 240 | DMA_SINC | DMA_SSIZE(3) | DMA_START; |
252 | } /* pcm_play_dma_start */ | 241 | } /* pcm_play_dma_start */ |
@@ -263,10 +252,6 @@ void pcm_play_dma_stop(void) | |||
263 | 252 | ||
264 | /* Reset the FIFO */ | 253 | /* Reset the FIFO */ |
265 | pcm_apply_settings(false); | 254 | pcm_apply_settings(false); |
266 | |||
267 | #ifdef HAVE_SPDIF_OUT | ||
268 | EBU1CONFIG = IIS_RESET | EBU_DEFPARM; | ||
269 | #endif | ||
270 | } /* pcm_play_dma_stop */ | 255 | } /* pcm_play_dma_stop */ |
271 | 256 | ||
272 | void pcm_init(void) | 257 | void pcm_init(void) |
@@ -291,6 +276,10 @@ void pcm_init(void) | |||
291 | /* Prevent pops (resets DAC to zero point) */ | 276 | /* Prevent pops (resets DAC to zero point) */ |
292 | SET_IIS_CONFIG(IIS_DEFPARM | IIS_RESET); | 277 | SET_IIS_CONFIG(IIS_DEFPARM | IIS_RESET); |
293 | 278 | ||
279 | #if defined(HAVE_SPDIF_IN) || defined(HAVE_SPDIF_OUT) | ||
280 | spdif_init(); | ||
281 | #endif | ||
282 | |||
294 | /* Initialize default register values. */ | 283 | /* Initialize default register values. */ |
295 | ac_init(); | 284 | ac_init(); |
296 | 285 | ||
@@ -417,11 +406,6 @@ void pcm_init_recording(void) | |||
417 | DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */ | 406 | DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */ |
418 | DMAROUTE = (DMAROUTE & 0xffff00ff) | DMA1_REQ_AUDIO_2; | 407 | DMAROUTE = (DMAROUTE & 0xffff00ff) | DMA1_REQ_AUDIO_2; |
419 | 408 | ||
420 | #ifdef HAVE_SPDIF_IN | ||
421 | /* PHASECONFIG setup: gain = 3*2^13, source = EBUIN */ | ||
422 | PHASECONFIG = (6 << 3) | (4 << 0); | ||
423 | #endif | ||
424 | |||
425 | pcm_rec_dma_stop(); | 409 | pcm_rec_dma_stop(); |
426 | 410 | ||
427 | ICR7 = (7 << 2); /* Enable interrupt at level 7, priority 0 */ | 411 | ICR7 = (7 << 2); /* Enable interrupt at level 7, priority 0 */ |
@@ -506,18 +490,12 @@ void pcm_play_pause_pause(void) | |||
506 | /* Disable DMA peripheral request. */ | 490 | /* Disable DMA peripheral request. */ |
507 | DCR0 &= ~DMA_EEXT; | 491 | DCR0 &= ~DMA_EEXT; |
508 | pcm_apply_settings(true); | 492 | pcm_apply_settings(true); |
509 | #ifdef HAVE_SPDIF_OUT | ||
510 | EBU1CONFIG = EBU_DEFPARM; | ||
511 | #endif | ||
512 | } /* pcm_play_pause_pause */ | 493 | } /* pcm_play_pause_pause */ |
513 | 494 | ||
514 | void pcm_play_pause_unpause(void) | 495 | void pcm_play_pause_unpause(void) |
515 | { | 496 | { |
516 | /* Enable the FIFO and force one write to it */ | 497 | /* Enable the FIFO and force one write to it */ |
517 | pcm_apply_settings(false); | 498 | pcm_apply_settings(false); |
518 | #ifdef HAVE_SPDIF_OUT | ||
519 | EBU1CONFIG = EBU_DEFPARM; | ||
520 | #endif | ||
521 | DCR0 |= DMA_EEXT | DMA_START; | 499 | DCR0 |= DMA_EEXT | DMA_START; |
522 | } /* pcm_play_pause_unpause */ | 500 | } /* pcm_play_pause_unpause */ |
523 | 501 | ||