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diff --git a/firmware/target/coldfire/mpio/system-mpio.c b/firmware/target/coldfire/mpio/system-mpio.c
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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2010 by Marcin Bukat
11 * Copyright (C) 2006 by Linus Nielsen Feltzing
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
17 *
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
20 *
21 ****************************************************************************/
22#include "config.h"
23#include "cpu.h"
24#include "kernel.h"
25#include "system.h"
26#include "power.h"
27#include "timer.h"
28
29/* Settings for all possible clock frequencies (with properly working timers)
30 * NOTE: Some 5249 chips don't like having PLLDIV set to 0. We must avoid that!
31 *
32 * xxx_REFRESH_TIMER below
33 * system.h, CPUFREQ_xxx_MULT |
34 * | |
35 * V V
36 * PLLCR & Refreshtim. IDECONFIG1/IDECONFIG2
37 * CPUCLK/Hz MULT ~0x70400000 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait
38 * ---------------------------------------------------------------------------------------
39 * 11289600 1 0x00800200 4 1 0x0180 0x0180 0x0180 1 1 0
40 * 22579200 2 0x0589e025 10 4 0x0180 0x0180 0x0180 1 1 0
41 * 33868800 3 0x0388e025 15 7 0x0180 0x0180 0x0180 1 1 0
42 * 45158400 4 0x0589e021 21 10 0x0580 0x0180 0x0580 1 1 0
43 * 56448000 5 0x0289e025 26 12 0x0580 0x0580 0x0980 2 1 0
44 * 67737600 6 0x0388e021 32 15 0x0980 0x0980 0x0d80 2 1 0
45 * 79027200 7 0x038a6021 37 18 0x0980 0x0d80 0x1180 2 1 0
46 * 90316800 8 0x038be021 43 21 0x0d80 0x0d80 0x1580 2 1 0
47 * 101606400 9 0x01892025 48 23 0x0d80 0x1180 0x1980 2 1 0
48 * 112896000 10 0x0189e025 54 26 0x1180 0x1580 0x1d80 3 1 0
49 * 124185600 11 0x018ae025 59 29 0x1180 0x1580 0x2180 3 1 1
50 */
51
52#define MAX_REFRESH_TIMER 59
53#define NORMAL_REFRESH_TIMER 21
54#define DEFAULT_REFRESH_TIMER 4
55
56#ifdef HAVE_ADJUSTABLE_CPU_FREQ
57void set_cpu_frequency (long) __attribute__ ((section (".icode")));
58void set_cpu_frequency(long frequency)
59#else
60void cf_set_cpu_frequency (long) __attribute__ ((section (".icode")));
61void cf_set_cpu_frequency(long frequency)
62#endif
63{
64 switch(frequency)
65 {
66 case CPUFREQ_MAX:
67 DCR = (0x8200 | DEFAULT_REFRESH_TIMER);
68 /* Refresh timer for bypass frequency */
69 PLLCR &= ~1; /* Bypass mode */
70 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
71 PLLCR = 0x018ae025 | (PLLCR & 0x70400000);
72 CSCR0 = 0x00001180; /* Flash: 4 wait states */
73 CSCR3 = 0x00000980; /* LCD: 2 wait states */
74 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
75 This may take up to 10ms! */
76 timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
77 DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
78 cpu_frequency = CPUFREQ_MAX;
79 IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(3<<10);
80 /* BUFEN2 enable on /CS2 | CS2Post 1 clock| CS2Pre 3 clocks*/
81 IDECONFIG2 = (1<<18)|(1<<16)|(1<<8)|(1<<0); /* TA /CS2 enable + CS2wait */
82
83 and_l(~(0x07<<16), &ADCONFIG);
84 or_l((0x05)<<16, &ADCONFIG); /* adclk = busclk/32 */
85 break;
86
87 case CPUFREQ_NORMAL:
88 DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
89 /* Refresh timer for bypass frequency */
90 PLLCR &= ~1; /* Bypass mode */
91 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
92 PLLCR = 0x0589e021 | (PLLCR & 0x70400000);
93 CSCR0 = 0x00000580; /* Flash: 1 wait state */
94 CSCR3 = 0x00000580; /* LCD: 1 wait state */
95 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
96 This may take up to 10ms! */
97 timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
98 DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
99 cpu_frequency = CPUFREQ_NORMAL;
100 IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10);
101 IDECONFIG2 = (1<<18)|(1<<16);
102
103 and_l(~(0x07<<16), &ADCONFIG);
104 or_l((0x03)<<16, &ADCONFIG); /* adclk = busclk/8 */
105 break;
106
107 default:
108 DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
109 /* Refresh timer for bypass frequency */
110 PLLCR &= ~1; /* Bypass mode */
111 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
112 /* Power down PLL, but keep CLSEL and CRSEL */
113 PLLCR = 0x00800200 | (PLLCR & 0x70400000);
114 CSCR0 = 0x00000180; /* Flash: 0 wait states */
115 CSCR3 = 0x00000180; /* LCD: 0 wait states */
116 DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
117 cpu_frequency = CPUFREQ_DEFAULT;
118 IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10);
119 IDECONFIG2 = (1<<18)|(1<<16);
120
121 and_l(~(0x07<<16), &ADCONFIG);
122 or_l((0x01)<<16, &ADCONFIG); /* adclk = busclk/2 */
123 break;
124 }
125}
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