diff options
Diffstat (limited to 'firmware/target/coldfire/mpio/hd200')
| -rw-r--r-- | firmware/target/coldfire/mpio/hd200/system-hd200.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/firmware/target/coldfire/mpio/hd200/system-hd200.c b/firmware/target/coldfire/mpio/hd200/system-hd200.c index a6277d0390..e46bbdb80b 100644 --- a/firmware/target/coldfire/mpio/hd200/system-hd200.c +++ b/firmware/target/coldfire/mpio/hd200/system-hd200.c | |||
| @@ -29,24 +29,24 @@ | |||
| 29 | /* Settings for all possible clock frequencies (with properly working timers) | 29 | /* Settings for all possible clock frequencies (with properly working timers) |
| 30 | * NOTE: Some 5249 chips don't like having PLLDIV set to 0. We must avoid that! | 30 | * NOTE: Some 5249 chips don't like having PLLDIV set to 0. We must avoid that! |
| 31 | * | 31 | * |
| 32 | * xxx_REFRESH_TIMER below | 32 | * xxx_REFRESH_TIMER below |
| 33 | * system.h, CPUFREQ_xxx_MULT | | 33 | * system.h, CPUFREQ_xxx_MULT | |
| 34 | * | | | 34 | * | | |
| 35 | * V V | 35 | * V V |
| 36 | * PLLCR & Rftim. IDECONFIG1/IDECONFIG2 | 36 | * PLLCR & Refreshtim. IDECONFIG1/IDECONFIG2 |
| 37 | * CPUCLK/Hz MULT ~0x70c00000 16MB CSCR0 CSCR1 CS2Pre CS2Post CS2Wait | 37 | * CPUCLK/Hz MULT ~0x70400000 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait |
| 38 | * ------------------------------------------------------------------------- | 38 | * --------------------------------------------------------------------------------------- |
| 39 | * 11289600 1 0x00000200 4 0x0180 0x0180 1 1 0 | 39 | * 11289600 1 0x00800200 4 1 0x0180 0x0180 0x0180 1 1 0 |
| 40 | * 22579200 2 0x05028049 10 0x0180 0x0180 1 1 0 | 40 | * 22579200 2 0x0589e025 10 4 0x0180 0x0180 0x0180 1 1 0 |
| 41 | * 33868800 3 0x03024049 15 0x0180 0x0180 1 1 0 | 41 | * 33868800 3 0x0388e025 15 7 0x0180 0x0180 0x0180 1 1 0 |
| 42 | * 45158400 4 0x05028045 21 0x0180 0x0180 1 1 0 | 42 | * 45158400 4 0x0589e021 21 10 0x0580 0x0180 0x0580 1 1 0 |
| 43 | * 56448000 5 0x02028049 26 0x0580 0x0580 2 1 0 | 43 | * 56448000 5 0x0289e025 26 12 0x0580 0x0580 0x0980 2 1 0 |
| 44 | * 67737600 6 0x03024045 32 0x0580 0x0980 2 1 0 | 44 | * 67737600 6 0x0388e021 32 15 0x0980 0x0980 0x0d80 2 1 0 |
| 45 | * 79027200 7 0x0302a045 37 0x0580 0x0d80 2 1 0 | 45 | * 79027200 7 0x038a6021 37 18 0x0980 0x0d80 0x1180 2 1 0 |
| 46 | * 90316800 8 0x03030045 43 0x0980 0x0d80 2 1 0 | 46 | * 90316800 8 0x038be021 43 21 0x0d80 0x0d80 0x1580 2 1 0 |
| 47 | * 101606400 9 0x01024049 48 0x0980 0x1180 2 1 0 | 47 | * 101606400 9 0x01892025 48 23 0x0d80 0x1180 0x1980 2 1 0 |
| 48 | * 112896000 10 0x01028049 54 0x0980 0x1580 3 1 0 | 48 | * 112896000 10 0x0189e025 54 26 0x1180 0x1580 0x1d80 3 1 0 |
| 49 | * 124185600 11 0x0102c049 59 0x0980 0x1180 3 1 1 | 49 | * 124185600 11 0x018ae025 59 29 0x1180 0x1580 0x2180 3 1 1 |
| 50 | */ | 50 | */ |
| 51 | 51 | ||
| 52 | #define MAX_REFRESH_TIMER 59 | 52 | #define MAX_REFRESH_TIMER 59 |