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Diffstat (limited to 'firmware/target/coldfire/mpio/hd200/system-hd200.c')
-rw-r--r--firmware/target/coldfire/mpio/hd200/system-hd200.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/firmware/target/coldfire/mpio/hd200/system-hd200.c b/firmware/target/coldfire/mpio/hd200/system-hd200.c
index 814cc718d4..beab29961d 100644
--- a/firmware/target/coldfire/mpio/hd200/system-hd200.c
+++ b/firmware/target/coldfire/mpio/hd200/system-hd200.c
@@ -7,7 +7,8 @@
7 * \/ \/ \/ \/ \/ 7 * \/ \/ \/ \/ \/
8 * $Id:$ 8 * $Id:$
9 * 9 *
10 * Copyright (C) 2010 Marcin Bukat 10 * Copyright (C) 2010 by Marcin Bukat
11 * Copyright (C) 2006 by Linus Nielsen Feltzing
11 * 12 *
12 * This program is free software; you can redistribute it and/or 13 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License 14 * modify it under the terms of the GNU General Public License
@@ -26,6 +27,7 @@
26#include "timer.h" 27#include "timer.h"
27 28
28/* Settings for all possible clock frequencies (with properly working timers) 29/* Settings for all possible clock frequencies (with properly working timers)
30 * NOTE: Some 5249 chips don't like having PLLDIV set to 0. We must avoid that!
29 * 31 *
30 * xxx_REFRESH_TIMER below 32 * xxx_REFRESH_TIMER below
31 * system.h, CPUFREQ_xxx_MULT | 33 * system.h, CPUFREQ_xxx_MULT |
@@ -66,7 +68,7 @@ void cf_set_cpu_frequency(long frequency)
66 /* Refresh timer for bypass frequency */ 68 /* Refresh timer for bypass frequency */
67 PLLCR &= ~1; /* Bypass mode */ 69 PLLCR &= ~1; /* Bypass mode */
68 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); 70 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
69 PLLCR = 0x0102c049 | (PLLCR & 0x70C00000); 71 PLLCR = 0x018ae025 | (PLLCR & 0x70400000);
70 CSCR0 = 0x00001180; /* Flash: 4 wait states */ 72 CSCR0 = 0x00001180; /* Flash: 4 wait states */
71 CSCR3 = 0x00000580; /* LCD: 4 wait states */ 73 CSCR3 = 0x00000580; /* LCD: 4 wait states */
72 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. 74 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -87,7 +89,7 @@ void cf_set_cpu_frequency(long frequency)
87 /* Refresh timer for bypass frequency */ 89 /* Refresh timer for bypass frequency */
88 PLLCR &= ~1; /* Bypass mode */ 90 PLLCR &= ~1; /* Bypass mode */
89 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); 91 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
90 PLLCR = 0x05028045 | (PLLCR & 0x70C00000); 92 PLLCR = 0x0589e021 | (PLLCR & 0x70400000);
91 CSCR0 = 0x00000580; /* Flash: 1 wait state */ 93 CSCR0 = 0x00000580; /* Flash: 1 wait state */
92 CSCR3 = 0x00000180; /* LCD: 0 wait states */ 94 CSCR3 = 0x00000180; /* LCD: 0 wait states */
93 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. 95 while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -108,7 +110,7 @@ void cf_set_cpu_frequency(long frequency)
108 PLLCR &= ~1; /* Bypass mode */ 110 PLLCR &= ~1; /* Bypass mode */
109 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); 111 timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
110 /* Power down PLL, but keep CLSEL and CRSEL */ 112 /* Power down PLL, but keep CLSEL and CRSEL */
111 PLLCR = 0x00000200 | (PLLCR & 0x70C00000); 113 PLLCR = 0x00800200 | (PLLCR & 0x70400000);
112 CSCR0 = 0x00000180; /* Flash: 0 wait states */ 114 CSCR0 = 0x00000180; /* Flash: 0 wait states */
113 CSCR3 = 0x00000180; /* LCD: 0 wait states */ 115 CSCR3 = 0x00000180; /* LCD: 0 wait states */
114 DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ 116 DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */