diff options
Diffstat (limited to 'firmware/target/coldfire/iriver/system-iriver.c')
-rw-r--r-- | firmware/target/coldfire/iriver/system-iriver.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c index 43ba4eeed4..63011969b4 100644 --- a/firmware/target/coldfire/iriver/system-iriver.c +++ b/firmware/target/coldfire/iriver/system-iriver.c | |||
@@ -81,7 +81,7 @@ void set_cpu_frequency(long frequency) | |||
81 | PLLCR &= ~1; /* Bypass mode */ | 81 | PLLCR &= ~1; /* Bypass mode */ |
82 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 82 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
83 | RECALC_DELAYS(CPUFREQ_MAX); | 83 | RECALC_DELAYS(CPUFREQ_MAX); |
84 | PLLCR = 0x01056005 | (PLLCR & 0x70c00000); | 84 | PLLCR = 0x01856005 | (PLLCR & 0x70400000); |
85 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | 85 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ |
86 | CSCR1 = 0x00001580; /* LCD: 5 wait states */ | 86 | CSCR1 = 0x00001580; /* LCD: 5 wait states */ |
87 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 87 | #if CONFIG_USBOTG == USBOTG_ISP1362 |
@@ -108,7 +108,7 @@ void set_cpu_frequency(long frequency) | |||
108 | PLLCR &= ~1; /* Bypass mode */ | 108 | PLLCR &= ~1; /* Bypass mode */ |
109 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 109 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
110 | RECALC_DELAYS(CPUFREQ_NORMAL); | 110 | RECALC_DELAYS(CPUFREQ_NORMAL); |
111 | PLLCR = 0x0305e005 | (PLLCR & 0x70c00000); | 111 | PLLCR = 0x0385e005 | (PLLCR & 0x70400000); |
112 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | 112 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ |
113 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 113 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
114 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 114 | #if CONFIG_USBOTG == USBOTG_ISP1362 |
@@ -134,8 +134,8 @@ void set_cpu_frequency(long frequency) | |||
134 | PLLCR &= ~1; /* Bypass mode */ | 134 | PLLCR &= ~1; /* Bypass mode */ |
135 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); | 135 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); |
136 | RECALC_DELAYS(CPUFREQ_DEFAULT); | 136 | RECALC_DELAYS(CPUFREQ_DEFAULT); |
137 | /* Power down PLL, but keep CLSEL and CRSEL */ | 137 | /* Power down PLL, but keep CLSEL */ |
138 | PLLCR = 0x00000200 | (PLLCR & 0x70c00000); | 138 | PLLCR = 0x00000200 | (PLLCR & 0x70400000); |
139 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | 139 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ |
140 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 140 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
141 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 141 | #if CONFIG_USBOTG == USBOTG_ISP1362 |