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Diffstat (limited to 'firmware/target/coldfire/iriver/h100/lcd-as-h100.S')
-rw-r--r--firmware/target/coldfire/iriver/h100/lcd-as-h100.S229
1 files changed, 105 insertions, 124 deletions
diff --git a/firmware/target/coldfire/iriver/h100/lcd-as-h100.S b/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
index 9ebb5752aa..b13d5146b9 100644
--- a/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
+++ b/firmware/target/coldfire/iriver/h100/lcd-as-h100.S
@@ -106,153 +106,134 @@ lcd_write_data:
106 * will occur. */ 106 * will occur. */
107 107
108lcd_grey_data: 108lcd_grey_data:
109 lea.l (-10*4, %sp), %sp 109 lea.l (-11*4, %sp), %sp
110 movem.l %d2-%d6/%a2-%a6, (%sp) /* free some registers */ 110 movem.l %d2-%d7/%a2-%a6, (%sp) /* free some registers */
111 movem.l (10*4+4, %sp), %a0-%a2 /* values, phases, length */ 111 movem.l (11*4+4, %sp), %a0-%a2 /* values, phases, length */
112 lea.l (%a1, %a2.l*4), %a2 /* end address */ 112 lea.l (%a1, %a2.l*4), %a2 /* end address */
113 moveq #8, %d1 113 moveq #8, %d1
114 or.l %d1, (MBAR2+0xb4) /* A0 = 1 (data) */ 114 or.l %d1, (MBAR2+0xb4) /* A0 = 1 (data) */
115 lea 0xf0000000, %a3 /* LCD data port */ 115 lea 0xf0000000, %a3 /* LCD data port */
116 116 moveq.l #24, %d6 /* shift count */
117 moveq.l #15, %d3 117 move.l #0xc30c3, %d7 /* bit shuffle factor */
118 add.l %a1, %d3 118
119 and.l #0xfffffff0, %d3 /* first line bound */ 119 moveq.l #12, %d2
120 move.l %a2, %d1 120 add.l %a1, %d2
121 and.l #0xfffffff0, %d1 /* last line bound */ 121 and.l #0xfffffff0, %d2 /* first line bound */
122 cmp.l %d3, %d1 122 cmp.l %d2, %a2 /* end address lower than first line bound? */
123 bls.w .g_tloop /* no lines to copy - jump to tail loop */ 123 bhs.s 1f
124 cmp.l %a1, %d0 124 move.l %a2, %d2 /* -> adjust end address of head loop */
125 bls.s .g_lloop /* no head blocks - jump to line loop */ 1251:
126 cmp.l %a1, %d2
127 bls.s .g_hend
126 128
127.g_hloop: 129.g_hloop:
128 move.l (%a1), %d2 /* fetch 4 pixel phases */ 130 move.l (%a1), %d0 /* fetch 4 pixel phases */
129 131
130 bclr.l #31, %d2 /* Z = !(p0 & 0x80); p0 &= ~0x80; */ 132 move.l %d0, %d1
131 seq.b %d0 /* %d0 = ........................00000000 */ 133 and.l #0x80808080, %d1 /* separate MSBs of the 4 phases */
132 lsl.l #2, %d0 /* %d0 = ......................00000000.. */ 134 eor.l %d1, %d0 /* clear them in %d0 */
133 bclr.l #23, %d2 /* Z = !(p1 & 0x80); p1 &= ~0x80; */ 135 add.l (%a0)+, %d0 /* add 4 pixel values to the phases */
134 seq.b %d0 /* %d0 = ......................0011111111 */ 136 move.l %d0, (%a1)+ /* store new phases, advance pointer */
135 lsl.l #2, %d0 /* %d0 = ....................0011111111.. */
136 bclr.l #15, %d2 /* Z = !(p2 & 0x80); p2 &= ~0x80; */
137 seq.b %d0 /* %d0 = ....................001122222222 */
138 lsl.l #2, %d0 /* %d0 = ..................001122222222.. */
139 bclr.l #7, %d2 /* Z = !(p3 & 0x80); p3 &= ~0x80; */
140 seq.b %d0 /* %d0 = ..................00112233333333 */
141 lsr.l #6, %d0 /* %d0 = ........................00112233 */
142 move.w %d0, (%a3) /* write pixel block */
143
144 add.l (%a0)+, %d2 /* add 4 pixel values to the phases */
145 move.l %d2, (%a1)+ /* store new phases, advance pointer */
146 137
147 cmp.l %a1, %d3 /* go up to first line bound */ 138 lsr.l #1, %d1 /* %d1 = .0.......1.......2.......3...... */
139 mulu.l %d7, %d1 /* %d1 = 00112233112233..2233....33...... */
140 not.l %d1 /* negate bits */
141 lsr.l %d6, %d1 /* %d1 = ........................00112233 */
142 move.w %d1, (%a3) /* write pixel block */
143
144 cmp.l %a1, %d2 /* go up to first line bound */
148 bhi.s .g_hloop 145 bhi.s .g_hloop
146
147.g_hend:
148 cmp.l %a1, %a2
149 bls.w .g_tend
150 lea.l (-12, %a2), %a2
151 cmp.l %a1, %a2
152 bls.s .g_lend
149 153
150.g_lloop: 154.g_lloop:
151 movem.l (%a1), %d2-%d5 /* fetch 4 blocks of 4 pixel phases each */ 155 movem.l (%a1), %d0-%d3 /* fetch 4 blocks of 4 pixel phases each */
152 156
153 bclr.l #31, %d2 /* calculate first pixel block */ 157 move.l %d0, %d4 /* calculate first pixel block */
154 seq.b %d0 158 and.l #0x80808080, %d4
155 lsl.l #2, %d0 159 eor.l %d4, %d0
156 bclr.l #23, %d2 160 lsr.l #1, %d4
157 seq.b %d0 161 mulu.l %d7, %d4
158 lsl.l #2, %d0 162 not.l %d4
159 bclr.l #15, %d2 163 lsr.l %d6, %d4
160 seq.b %d0 164
161 lsl.l #2, %d0 165 move.w %d4, (%a3) /* write first pixel block to LCD */
162 bclr.l #7, %d2 166
163 seq.b %d0 167 move.l %d1, %d5 /* calculate second pixel block */
164 lsr.l #6, %d0 168 and.l #0x80808080, %d5
165 169 eor.l %d5, %d1
166 move.w %d0, (%a3) /* write first block to LCD */ 170 lsr.l #1, %d5
167 171 mulu.l %d7, %d5
168 bclr.l #31, %d3 /* calculate second pixel block */ 172 not.l %d5
169 seq.b %d6 173 lsr.l %d6, %d5
170 lsl.l #2, %d6 174
171 bclr.l #23, %d3 175 move.l %d2, %d4 /* calculate third pixel block */
172 seq.b %d6 176 and.l #0x80808080, %d4
173 lsl.l #2, %d6 177 eor.l %d4, %d2
174 bclr.l #15, %d3 178 lsr.l #1, %d4
175 seq.b %d6 179 mulu.l %d7, %d4
176 lsl.l #2, %d6 180 not.l %d4
177 bclr.l #7, %d3 181 lsr.l %d6, %d4
178 seq.b %d6 182
179 lsr.l #6, %d6 183 move.w %d5, (%a3) /* write second pixel block to LCD */
180 184
181 bclr.l #31, %d4 /* calculate third pixel block */ 185 movem.l (%a0), %d5/%a4-%a6 /* fetch 4 blocks of 4 pixel values each */
182 seq.b %d0
183 lsl.l #2, %d0
184 bclr.l #23, %d4
185 seq.b %d0
186 lsl.l #2, %d0
187 bclr.l #15, %d4
188 seq.b %d0
189 lsl.l #2, %d0
190 bclr.l #7, %d4
191 seq.b %d0
192 lsr.l #6, %d0
193
194 move.w %d6, (%a3) /* write second block to LCD */
195
196 movem.l (%a0), %d6/%a4-%a6 /* fetch 4 blocks of 4 pixel values each */
197 lea.l (16, %a0), %a0 186 lea.l (16, %a0), %a0
198 187
199 move.w %d0, (%a3) /* write third block to LCD */ 188 move.w %d4, (%a3) /* write third pixel block to LCD */
200 189
201 bclr.l #31, %d5 /* calculate fourth pixel block */ 190 move.l %d3, %d4 /* calculate fourth pixel block */
202 seq.b %d0 191 and.l #0x80808080, %d4
203 lsl.l #2, %d0 192 eor.l %d4, %d3
204 bclr.l #23, %d5 193 lsr.l #1, %d4
205 seq.b %d0 194 mulu.l %d7, %d4
206 lsl.l #2, %d0 195 not.l %d4
207 bclr.l #15, %d5 196 lsr.l %d6, %d4
208 seq.b %d0 197
209 lsl.l #2, %d0 198 add.l %d5, %d0 /* calculate 4*4 new pixel phases */
210 bclr.l #7, %d5 199 add.l %a4, %d1 /* (packed addition) */
211 seq.b %d0 200 add.l %a5, %d2
212 lsr.l #6, %d0 201 add.l %a6, %d3
213 202
214 add.l %d6, %d2 /* calculate 4*4 new pixel phases */ 203 movem.l %d0-%d3, (%a1) /* store 4*4 new pixel phases */
215 add.l %a4, %d3 /* (packed addition) */
216 add.l %a5, %d4
217 add.l %a6, %d5
218
219 movem.l %d2-%d5, (%a1) /* store 4*4 new pixel phases */
220 lea.l (16, %a1), %a1 204 lea.l (16, %a1), %a1
221 205
222 move.w %d0, (%a3) /* write fourth block to LCD */ 206 move.w %d4, (%a3) /* write fourth pixel block to LCD */
223 207
224 cmp.l %a1, %d1 /* go up to last line bound */ 208 cmp.l %a1, %a2 /* go up to last line bound */
225 bhi.w .g_lloop 209 bhi.s .g_lloop
226 210
211.g_lend:
212 lea.l (12, %a2), %a2
227 cmp.l %a1, %a2 213 cmp.l %a1, %a2
228 bls.s .g_no_tail 214 bls.s .g_tend
229 215
230.g_tloop: 216.g_tloop:
231 move.l (%a1), %d2 217 move.l (%a1), %d0 /* fetch 4 pixel phases */
232 218
233 bclr.l #31, %d2 219 move.l %d0, %d1
234 seq.b %d0 220 and.l #0x80808080, %d1
235 lsl.l #2, %d0 221 eor.l %d1, %d0
236 bclr.l #23, %d2 222 add.l (%a0)+, %d0 /* add 4 pixel values to the phases */
237 seq.b %d0 223 move.l %d0, (%a1)+ /* store new phases, advance pointer */
238 lsl.l #2, %d0 224
239 bclr.l #15, %d2 225 lsr.l #1, %d1
240 seq.b %d0 226 mulu.l %d7, %d1
241 lsl.l #2, %d0 227 not.l %d1
242 bclr.l #7, %d2 228 lsr.l %d6, %d1
243 seq.b %d0 229 move.w %d1, (%a3) /* write pixel block */
244 lsr.l #6, %d0
245 move.w %d0, (%a3)
246
247 add.l (%a0)+, %d2
248 move.l %d2, (%a1)+
249 230
250 cmp.l %a1, %a2 /* go up to end address */ 231 cmp.l %a1, %a2 /* go up to end address */
251 bhi.s .g_tloop 232 bhi.s .g_tloop
252 233
253.g_no_tail: 234.g_tend:
254 movem.l (%sp), %d2-%d6/%a2-%a6 /* restore registers */ 235 movem.l (%sp), %d2-%d7/%a2-%a6 /* restore registers */
255 lea.l (10*4, %sp), %sp 236 lea.l (11*4, %sp), %sp
256 rts 237 rts
257 238
258.gd_end: 239.gd_end:
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-05 15:11:14 +0000