diff options
Diffstat (limited to 'firmware/target/coldfire/iaudio/m3/adc-m3.c')
-rw-r--r-- | firmware/target/coldfire/iaudio/m3/adc-m3.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/firmware/target/coldfire/iaudio/m3/adc-m3.c b/firmware/target/coldfire/iaudio/m3/adc-m3.c index b0d7f7430b..1f17b1e3f1 100644 --- a/firmware/target/coldfire/iaudio/m3/adc-m3.c +++ b/firmware/target/coldfire/iaudio/m3/adc-m3.c | |||
@@ -51,8 +51,8 @@ void IIC2(void) | |||
51 | 51 | ||
52 | MBSR2 &= ~IFF; /* Clear interrupt flag */ | 52 | MBSR2 &= ~IFF; /* Clear interrupt flag */ |
53 | 53 | ||
54 | if (MBSR2 & IAL) /* Arbitration lost - shouldn't happen */ | 54 | if (MBSR2 & IAL) /* Arbitration lost - shouldn't never happen */ |
55 | { /* normally, but CPU freq change might induce it */ | 55 | { |
56 | MBSR2 &= ~IAL; /* Clear flag */ | 56 | MBSR2 &= ~IAL; /* Clear flag */ |
57 | MBCR2 &= ~MSTA; /* STOP */ | 57 | MBCR2 &= ~MSTA; /* STOP */ |
58 | } | 58 | } |
@@ -97,7 +97,6 @@ void adc_init(void) | |||
97 | MBSR2 = 0; /* Clear flags */ | 97 | MBSR2 = 0; /* Clear flags */ |
98 | MBCR2 = (IEN|IIEN); /* Enable interrupts */ | 98 | MBCR2 = (IEN|IIEN); /* Enable interrupts */ |
99 | 99 | ||
100 | and_l(~0x0f000000, &INTPRI8); | ||
101 | or_l( 0x04000000, &INTPRI8); /* INT62 - Priority 4 */ | 100 | or_l( 0x04000000, &INTPRI8); /* INT62 - Priority 4 */ |
102 | 101 | ||
103 | tick_add_task(adc_tick); | 102 | tick_add_task(adc_tick); |
@@ -105,3 +104,15 @@ void adc_init(void) | |||
105 | while (!data_ready) | 104 | while (!data_ready) |
106 | sleep(1); /* Ensure valid readings when adc_init returns */ | 105 | sleep(1); /* Ensure valid readings when adc_init returns */ |
107 | } | 106 | } |
107 | |||
108 | /* The ADC (most probably the PIC12F675) obviously has a slow and buggy I²C | ||
109 | * implementation. If a transfer is stopped prematurely, it often locks up | ||
110 | * and doesn't react anymore until the unit is power cycled. */ | ||
111 | |||
112 | void adc_close(void) | ||
113 | { | ||
114 | tick_remove_task(adc_tick); | ||
115 | |||
116 | while (MBSR2 & IBB) /* Wait for an ongoing transfer to finish */ | ||
117 | sleep(1); | ||
118 | } | ||