diff options
Diffstat (limited to 'firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S')
| -rw-r--r-- | firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S | 54 |
1 files changed, 35 insertions, 19 deletions
diff --git a/firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S b/firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S index d92d7e6857..8ac49c4eaa 100644 --- a/firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S +++ b/firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S | |||
| @@ -58,15 +58,15 @@ | |||
| 58 | swap %d3 /* Shift data to upper byte */ | 58 | swap %d3 /* Shift data to upper byte */ |
| 59 | lsl.l #8, %d3 | 59 | lsl.l #8, %d3 |
| 60 | 60 | ||
| 61 | eor.l %d7, %d0 /* precalculate opposite state of clock line */ | 61 | move.l %d0, %d1 /* precalculate opposite state of clock line */ |
| 62 | eor.l %d7, %d1 | ||
| 62 | 63 | ||
| 63 | lsl.l #1,%d3 /* Shift out MSB */ | 64 | lsl.l #1, %d3 /* Shift out MSB */ |
| 64 | bcc.s 1f | 65 | bcc.s 1f |
| 65 | eor.l %d6, %d0 /* 1: Flip data bit */ | 66 | eor.l %d6, %d0 /* 1: Flip data bit */ |
| 67 | eor.l %d6, %d1 | ||
| 66 | 1: | 68 | 1: |
| 67 | move.l %d0, (%a0) /* Output new state and set CLK = 0*/ | 69 | move.l %d1, (%a0) /* Output new state and set CLK = 0*/ |
| 68 | move.l %d0, %d1 | ||
| 69 | eor.l %d7, %d1 | ||
| 70 | bra.w .wr_bit7 | 70 | bra.w .wr_bit7 |
| 71 | 71 | ||
| 72 | 72 | ||
| @@ -98,62 +98,77 @@ | |||
| 98 | eor.l %d1, %d3 /* previous state, and 0's where it doesn't */ | 98 | eor.l %d1, %d3 /* previous state, and 0's where it doesn't */ |
| 99 | swap %d3 /* Shift data to upper word */ | 99 | swap %d3 /* Shift data to upper word */ |
| 100 | 100 | ||
| 101 | eor.l %d7, %d0 /* precalculate opposite state of clock line */ | 101 | move.l %d0, %d1 /* precalculate opposite state of clock line */ |
| 102 | eor.l %d7, %d1 | ||
| 102 | 103 | ||
| 103 | lsl.l #1,%d3 /* Shift out MSB */ | 104 | lsl.l #1, %d3 /* Shift out MSB */ |
| 104 | bcc.s 1f | 105 | bcc.s 1f |
| 105 | eor.l %d6, %d0 /* 1: Flip data bit */ | 106 | eor.l %d6, %d0 /* 1: Flip data bit */ |
| 107 | eor.l %d6, %d1 | ||
| 106 | 1: | 108 | 1: |
| 107 | move.l %d0, (%a0) /* Output new state and set CLK = 0*/ | 109 | move.l %d1, (%a0) /* Output new state and set CLK = 0*/ |
| 108 | move.l %d0, %d1 | ||
| 109 | eor.l %d7, %d1 | ||
| 110 | nop | ||
| 111 | 110 | ||
| 112 | .macro bit_out | 111 | .macro bit_out |
| 113 | lsl.l #1,%d3 | 112 | move.l %d0, (%a0) /* Set CLK = 1 */ |
| 113 | lsl.l #1, %d3 | ||
| 114 | bcc.s 1f | 114 | bcc.s 1f |
| 115 | eor.l %d6, %d0 | 115 | eor.l %d6, %d0 |
| 116 | eor.l %d6, %d1 | ||
| 116 | 1: | 117 | 1: |
| 117 | move.l %d1, (%a0) /* Set CLK = 1 (delayed) */ | 118 | move.l %d1, (%a0) |
| 118 | move.l %d0, (%a0) | ||
| 119 | move.l %d0, %d1 | ||
| 120 | eor.l %d7, %d1 | ||
| 121 | .endm | 119 | .endm |
| 122 | bit_out | 120 | |
| 121 | nop | ||
| 123 | nop | 122 | nop |
| 124 | bit_out | 123 | bit_out |
| 125 | nop | 124 | nop |
| 125 | nop | ||
| 126 | bit_out | 126 | bit_out |
| 127 | nop | 127 | nop |
| 128 | nop | ||
| 128 | bit_out | 129 | bit_out |
| 129 | nop | 130 | nop |
| 131 | nop | ||
| 130 | bit_out | 132 | bit_out |
| 131 | nop | 133 | nop |
| 134 | nop | ||
| 132 | bit_out | 135 | bit_out |
| 133 | nop | 136 | nop |
| 137 | nop | ||
| 134 | bit_out | 138 | bit_out |
| 135 | nop | 139 | nop |
| 140 | nop | ||
| 136 | bit_out | 141 | bit_out |
| 137 | nop | 142 | nop |
| 143 | nop | ||
| 144 | bit_out | ||
| 138 | 145 | ||
| 146 | nop | ||
| 139 | .wr_bit7: | 147 | .wr_bit7: |
| 148 | nop | ||
| 140 | bit_out | 149 | bit_out |
| 141 | nop | 150 | nop |
| 151 | nop | ||
| 142 | bit_out | 152 | bit_out |
| 143 | nop | 153 | nop |
| 154 | nop | ||
| 144 | bit_out | 155 | bit_out |
| 145 | nop | 156 | nop |
| 157 | nop | ||
| 146 | bit_out | 158 | bit_out |
| 147 | nop | 159 | nop |
| 160 | nop | ||
| 148 | bit_out | 161 | bit_out |
| 149 | nop | 162 | nop |
| 163 | nop | ||
| 150 | bit_out | 164 | bit_out |
| 151 | nop | 165 | nop |
| 166 | nop | ||
| 152 | bit_out | 167 | bit_out |
| 153 | nop | 168 | nop |
| 154 | |||
| 155 | nop | 169 | nop |
| 156 | move.l %d1, (%a0) /* Set CLK = 1 (delayed) */ | 170 | |
| 171 | move.l %d0, (%a0) /* Set CLK = 1 */ | ||
| 157 | move.w %d2, %sr | 172 | move.w %d2, %sr |
| 158 | rts | 173 | rts |
| 159 | 174 | ||
| @@ -195,6 +210,7 @@ | |||
| 195 | move.l %d1, (%a0) /* Output new state and set CLK = 0*/ | 210 | move.l %d1, (%a0) /* Output new state and set CLK = 0*/ |
| 196 | move.l %d0, (%a0) /* set CLK = 1 */ | 211 | move.l %d0, (%a0) /* set CLK = 1 */ |
| 197 | .endm | 212 | .endm |
| 213 | |||
| 198 | bit_out_fast | 214 | bit_out_fast |
| 199 | bit_out_fast | 215 | bit_out_fast |
| 200 | bit_out_fast | 216 | bit_out_fast |