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path: root/firmware/target/coldfire/crt0.S
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Diffstat (limited to 'firmware/target/coldfire/crt0.S')
-rw-r--r--firmware/target/coldfire/crt0.S53
1 files changed, 51 insertions, 2 deletions
diff --git a/firmware/target/coldfire/crt0.S b/firmware/target/coldfire/crt0.S
index e6717710b1..881fcf908f 100644
--- a/firmware/target/coldfire/crt0.S
+++ b/firmware/target/coldfire/crt0.S
@@ -26,11 +26,51 @@
26 .global start 26 .global start
27start: 27start:
28 28
29#if defined(BOOTLOADER) && defined(HAVE_DUALBOOT) \
30 && (defined(IAUDIO_X5) || defined(IAUDIO_M5))
31
32 /* 8 byte dualboot signature */
33 bra.b 1f /* 0x6006 */
34 .short 0x4442 /* DB */
35#if defined(IAUDIO_X5)
36 .long 0x69617835 /* iax5 */
37#elif defined(IAUDIO_M5)
38 .long 0x69616d35 /* iam5 */
39#else
40#error Dualboot signature not defined
41#endif
421:
43 /* As the control registers are write-only, we're relying on MBAR2 being */
44 /* set up correctly by the preloader for button check */
45 /* Only use scratch regs until we're sure that we will boot rockbox */
46 lea MBAR2, %a1
47 move.l (%a1), %a0 /* store GPIO_READ result for button check in main() */
48
49 /* Wait ~3 seconds for ON-button release. We need roughly 300ns per
50 iteration, so we check 10000000 times to reach the desired delay */
51 move.l #10000000, %d0
52.on_button_test:
53 move.l (%a1), %d1 /* GPIO_READ */
54 and.l #0x06000000, %d1 /* Check main (bit 25=0) and remote (bit 26=0) */
55 cmp.l #0x06000000, %d1 /* ON buttons simultaneously */
56 beq.b .loadrockbox
57 subq.l #1, %d0
58 bne.b .on_button_test
59
60.loadoriginal:
61 jmp 0x10010
62
63.loadrockbox:
64 move.l %a0, %d7 /* keep initial GPIO_READ value in %d7 for now */
65
66#endif /* defined(BOOTLOADER && defined(HAVE_DUALBOOT)
67 && (defined(IAUDIO_X5) || defined(IAUDIO_M5)) */
68
29 move.w #0x2700,%sr 69 move.w #0x2700,%sr
30 70
31 move.l #vectors,%d0 71 move.l #vectors,%d0
32 movec.l %d0,%vbr 72 movec.l %d0,%vbr
33 73
34 move.l #MBAR+1,%d0 74 move.l #MBAR+1,%d0
35 movec.l %d0,%mbar 75 movec.l %d0,%mbar
36 76
@@ -39,7 +79,12 @@ start:
39 79
40 lea MBAR,%a0 80 lea MBAR,%a0
41 lea MBAR2,%a1 81 lea MBAR2,%a1
42 82
83#if defined(BOOTLOADER) && !defined(HAVE_DUALBOOT) \
84 && (defined(IAUDIO_X5) || defined(IAUDIO_M5))
85 move.l (%a1), %d7 /* store GPIO_READ result for button check in main() */
86#endif
87
43 clr.l (0x180,%a1) /* PLLCR = 0 */ 88 clr.l (0x180,%a1) /* PLLCR = 0 */
44 89
45 /* 64K DMA-capable SRAM at 0x10000000 90 /* 64K DMA-capable SRAM at 0x10000000
@@ -318,6 +363,10 @@ start:
318 move.l %d0,(%a2)+ 363 move.l %d0,(%a2)+
319 cmp.l %a2,%a4 364 cmp.l %a2,%a4
320 bhi.b .mungeloop 365 bhi.b .mungeloop
366
367#if defined(BOOTLOADER) && (defined(IAUDIO_X5) || defined(IAUDIO_M5))
368 move.l %d7, initial_gpio_read
369#endif
321 370
322 jsr main 371 jsr main
323.hoo: 372.hoo: