diff options
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/s5l8702/kernel-s5l8702.c | 11 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/system-s5l8702.c | 3 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/timer-s5l8702.c | 33 |
3 files changed, 24 insertions, 23 deletions
diff --git a/firmware/target/arm/s5l8702/kernel-s5l8702.c b/firmware/target/arm/s5l8702/kernel-s5l8702.c index b39b384696..6a70981c93 100644 --- a/firmware/target/arm/s5l8702/kernel-s5l8702.c +++ b/firmware/target/arm/s5l8702/kernel-s5l8702.c | |||
@@ -39,19 +39,16 @@ void tick_start(unsigned int interval_in_ms) | |||
39 | { | 39 | { |
40 | int cycles = 10 * interval_in_ms; | 40 | int cycles = 10 * interval_in_ms; |
41 | 41 | ||
42 | /* configure timer for 10 kHz (external source) */ | 42 | /* configure timer for 10 kHz (12 MHz / 16 / 75) */ |
43 | TBCMD = (1 << 1); /* TB_CLR */ | 43 | TBCMD = (1 << 1); /* TB_CLR */ |
44 | TBPRE = 75 - 1; /* prescaler */ /* 12 MHz / 16 / 75 = 10 KHz */ | 44 | TBPRE = 75 - 1; /* prescaler */ |
45 | TBCON = (0 << 13) | /* TB_INT1_EN */ | 45 | TBCON = (0 << 13) | /* TB_INT1_EN */ |
46 | (1 << 12) | /* TB_INT0_EN */ | 46 | (1 << 12) | /* TB_INT0_EN */ |
47 | (0 << 11) | /* TB_START */ | 47 | (0 << 11) | /* TB_START */ |
48 | (2 << 8) | /* TB_CS = PCLK / 16 */ | 48 | (2 << 8) | /* TB_CS = ECLK / 16 */ |
49 | (1 << 6) | /* UNKNOWN bit */ /* external 12 MHz clock (?) */ | 49 | (1 << 6) | /* select ECLK (12 MHz) */ |
50 | (0 << 4); /* TB_MODE_SEL = interval mode */ | 50 | (0 << 4); /* TB_MODE_SEL = interval mode */ |
51 | TBDATA0 = cycles; /* set interval period */ | 51 | TBDATA0 = cycles; /* set interval period */ |
52 | TBCMD = (1 << 0); /* TB_EN */ | 52 | TBCMD = (1 << 0); /* TB_EN */ |
53 | |||
54 | /* enable timer interrupt */ | ||
55 | VIC0INTENABLE = 1 << IRQ_TIMER; | ||
56 | } | 53 | } |
57 | 54 | ||
diff --git a/firmware/target/arm/s5l8702/system-s5l8702.c b/firmware/target/arm/s5l8702/system-s5l8702.c index 09aff3d84e..5b03f3bc5c 100644 --- a/firmware/target/arm/s5l8702/system-s5l8702.c +++ b/firmware/target/arm/s5l8702/system-s5l8702.c | |||
@@ -134,7 +134,7 @@ void INT_TIMER32(void) ICODE_ATTR; | |||
134 | void INT_TIMER32() | 134 | void INT_TIMER32() |
135 | { | 135 | { |
136 | uint32_t tstat = TSTAT; | 136 | uint32_t tstat = TSTAT; |
137 | /*if ((TECON >> 12) & 0x7 & (tstat >> 24)) INT_TIMERE();*/ | 137 | if ((TECON >> 12) & 0x7 & (tstat >> 24)) INT_TIMERE(); |
138 | if ((TFCON >> 12) & 0x7 & (tstat >> 16)) INT_TIMERF(); | 138 | if ((TFCON >> 12) & 0x7 & (tstat >> 16)) INT_TIMERF(); |
139 | if ((TGCON >> 12) & 0x7 & (tstat >> 8)) INT_TIMERG(); | 139 | if ((TGCON >> 12) & 0x7 & (tstat >> 8)) INT_TIMERG(); |
140 | if ((THCON >> 12) & 0x7 & tstat) INT_TIMERH(); | 140 | if ((THCON >> 12) & 0x7 & tstat) INT_TIMERH(); |
@@ -226,6 +226,7 @@ void system_init(void) | |||
226 | VIC0INTENABLE = 1 << IRQ_WHEEL; | 226 | VIC0INTENABLE = 1 << IRQ_WHEEL; |
227 | VIC0INTENABLE = 1 << IRQ_ATA; | 227 | VIC0INTENABLE = 1 << IRQ_ATA; |
228 | VIC1INTENABLE = 1 << (IRQ_MMC - 32); | 228 | VIC1INTENABLE = 1 << (IRQ_MMC - 32); |
229 | VIC0INTENABLE = 1 << IRQ_TIMER; | ||
229 | VIC0INTENABLE = 1 << IRQ_TIMER32; | 230 | VIC0INTENABLE = 1 << IRQ_TIMER32; |
230 | } | 231 | } |
231 | 232 | ||
diff --git a/firmware/target/arm/s5l8702/timer-s5l8702.c b/firmware/target/arm/s5l8702/timer-s5l8702.c index 7c69ab123a..5b145ed7e3 100644 --- a/firmware/target/arm/s5l8702/timer-s5l8702.c +++ b/firmware/target/arm/s5l8702/timer-s5l8702.c | |||
@@ -38,8 +38,10 @@ void INT_TIMERF(void) | |||
38 | 38 | ||
39 | bool timer_set(long cycles, bool start) | 39 | bool timer_set(long cycles, bool start) |
40 | { | 40 | { |
41 | int tf_en = TFCMD & (1 << 0); /* save TF_EN status */ | ||
42 | |||
41 | /* stop timer */ | 43 | /* stop timer */ |
42 | TFCMD = (0 << 0); /* TF_ENABLE */ | 44 | TFCMD = (0 << 0); /* TF_EN = disable */ |
43 | 45 | ||
44 | /* optionally unregister any previously registered timer user */ | 46 | /* optionally unregister any previously registered timer user */ |
45 | if (start) { | 47 | if (start) { |
@@ -49,33 +51,34 @@ bool timer_set(long cycles, bool start) | |||
49 | } | 51 | } |
50 | } | 52 | } |
51 | 53 | ||
52 | /* There is an odd behaviour when the 32-bit timers are launched | ||
53 | for the first time, the interrupt status bits are set and an | ||
54 | unexpected interrupt is generated if they are enabled. A way to | ||
55 | workaround this is to write the data registers before clearing | ||
56 | the counter. */ | ||
57 | TFDATA0 = cycles; | ||
58 | TFCMD = (1 << 1); /* TF_CLR */ | ||
59 | |||
60 | /* configure timer */ | 54 | /* configure timer */ |
61 | TFCON = (1 << 12) | /* TF_INT0_EN */ | 55 | TFCON = (1 << 12) | /* TF_INT0_EN */ |
62 | (4 << 8) | /* TF_CS, 4 = ECLK / 1 */ | 56 | (4 << 8) | /* TF_CS = ECLK / 1 */ |
63 | (1 << 6) | /* use ECLK (12MHz) */ | 57 | (1 << 6) | /* select ECLK (12 MHz) */ |
64 | (0 << 4); /* TF_MODE_SEL, 0 = interval mode */ | 58 | (0 << 4); /* TF_MODE_SEL = interval mode */ |
65 | TFPRE = 0; /* no prescaler */ | 59 | TFPRE = 0; /* no prescaler */ |
60 | TFDATA0 = cycles; /* set interval period */ | ||
66 | 61 | ||
67 | TFCMD = (1 << 0); /* TF_ENABLE */ | 62 | /* After the configuration, we must write '1' in TF_CLR to |
63 | * initialize the timer (s5l8700 DS): | ||
64 | * - Clear the counter register. | ||
65 | * - The value of TF_START is set to TF_OUT. | ||
66 | * - TF_DATA0 and TF_DATA1 are updated to the internal buffers. | ||
67 | * - Initialize the state of the previously captured signal. | ||
68 | */ | ||
69 | TFCMD = (1 << 1) | /* TF_CLR = initialize timer */ | ||
70 | (tf_en << 0); /* TF_EN = restore previous status */ | ||
68 | 71 | ||
69 | return true; | 72 | return true; |
70 | } | 73 | } |
71 | 74 | ||
72 | bool timer_start(void) | 75 | bool timer_start(void) |
73 | { | 76 | { |
74 | TFCMD = (1 << 0); /* TF_ENABLE */ | 77 | TFCMD = (1 << 0); /* TF_EN = enable */ |
75 | return true; | 78 | return true; |
76 | } | 79 | } |
77 | 80 | ||
78 | void timer_stop(void) | 81 | void timer_stop(void) |
79 | { | 82 | { |
80 | TFCMD = (0 << 0); /* TF_ENABLE */ | 83 | TFCMD = (0 << 0); /* TF_EN = disable */ |
81 | } | 84 | } |