diff options
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/i2c-pp.c | 12 | ||||
-rw-r--r-- | firmware/target/arm/ipod/backlight-nano_video.c | 8 | ||||
-rw-r--r-- | firmware/target/arm/ipod/video/lcd-video.c | 10 | ||||
-rw-r--r-- | firmware/target/arm/pcm-pp.c | 16 | ||||
-rw-r--r-- | firmware/target/arm/pnx0101/iriver-ifp7xx/power-ifp7xx.c | 5 | ||||
-rw-r--r-- | firmware/target/arm/pnx0101/system-pnx0101.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | 12 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/timer-meg-fx.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/system-arm.h | 97 | ||||
-rw-r--r-- | firmware/target/arm/tatung/tpj1022/backlight-tpj1022.c | 8 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/dsp-dm320.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/timer-dm320.c | 4 |
12 files changed, 115 insertions, 69 deletions
diff --git a/firmware/target/arm/i2c-pp.c b/firmware/target/arm/i2c-pp.c index 1cfbfaeff1..450effc32d 100644 --- a/firmware/target/arm/i2c-pp.c +++ b/firmware/target/arm/i2c-pp.c | |||
@@ -60,7 +60,7 @@ static int pp_i2c_read_byte(unsigned int addr, unsigned int *data) | |||
60 | 60 | ||
61 | { | 61 | { |
62 | unsigned int byte; | 62 | unsigned int byte; |
63 | int old_irq_level = set_irq_level(HIGHEST_IRQ_LEVEL); | 63 | int old_irq_level = disable_irq_save(); |
64 | 64 | ||
65 | /* clear top 15 bits, left shift 1, or in 0x1 for a read */ | 65 | /* clear top 15 bits, left shift 1, or in 0x1 for a read */ |
66 | I2C_ADDR = ((addr << 17) >> 16) | 0x1 ; | 66 | I2C_ADDR = ((addr << 17) >> 16) | 0x1 ; |
@@ -69,19 +69,19 @@ static int pp_i2c_read_byte(unsigned int addr, unsigned int *data) | |||
69 | 69 | ||
70 | I2C_CTRL |= I2C_SEND; | 70 | I2C_CTRL |= I2C_SEND; |
71 | 71 | ||
72 | set_irq_level(old_irq_level); | 72 | restore_irq(old_irq_level); |
73 | if (pp_i2c_wait_not_busy() < 0) | 73 | if (pp_i2c_wait_not_busy() < 0) |
74 | { | 74 | { |
75 | return -1; | 75 | return -1; |
76 | } | 76 | } |
77 | old_irq_level = set_irq_level(HIGHEST_IRQ_LEVEL); | 77 | old_irq_level = disable_irq_save(); |
78 | 78 | ||
79 | byte = I2C_DATA(0); | 79 | byte = I2C_DATA(0); |
80 | 80 | ||
81 | if (data) | 81 | if (data) |
82 | *data = byte; | 82 | *data = byte; |
83 | 83 | ||
84 | set_irq_level(old_irq_level); | 84 | restore_irq(old_irq_level); |
85 | } | 85 | } |
86 | 86 | ||
87 | return 0; | 87 | return 0; |
@@ -102,7 +102,7 @@ static int pp_i2c_send_bytes(unsigned int addr, unsigned int len, unsigned char | |||
102 | } | 102 | } |
103 | 103 | ||
104 | { | 104 | { |
105 | int old_irq_level = set_irq_level(HIGHEST_IRQ_LEVEL); | 105 | int old_irq_level = disable_irq_save(); |
106 | 106 | ||
107 | /* clear top 15 bits, left shift 1 */ | 107 | /* clear top 15 bits, left shift 1 */ |
108 | I2C_ADDR = (addr << 17) >> 16; | 108 | I2C_ADDR = (addr << 17) >> 16; |
@@ -118,7 +118,7 @@ static int pp_i2c_send_bytes(unsigned int addr, unsigned int len, unsigned char | |||
118 | 118 | ||
119 | I2C_CTRL |= I2C_SEND; | 119 | I2C_CTRL |= I2C_SEND; |
120 | 120 | ||
121 | set_irq_level(old_irq_level); | 121 | restore_irq(old_irq_level); |
122 | } | 122 | } |
123 | 123 | ||
124 | return 0x0; | 124 | return 0x0; |
diff --git a/firmware/target/arm/ipod/backlight-nano_video.c b/firmware/target/arm/ipod/backlight-nano_video.c index 6d77e2bd03..647bab9ac6 100644 --- a/firmware/target/arm/ipod/backlight-nano_video.c +++ b/firmware/target/arm/ipod/backlight-nano_video.c | |||
@@ -43,11 +43,11 @@ void _backlight_set_brightness(int val) | |||
43 | { | 43 | { |
44 | do | 44 | do |
45 | { | 45 | { |
46 | oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL); | 46 | oldlevel = disable_irq_save(); |
47 | GPIO_CLEAR_BITWISE(GPIOD_OUTPUT_VAL, 0x80); | 47 | GPIO_CLEAR_BITWISE(GPIOD_OUTPUT_VAL, 0x80); |
48 | udelay(10); | 48 | udelay(10); |
49 | GPIO_SET_BITWISE(GPIOD_OUTPUT_VAL, 0x80); | 49 | GPIO_SET_BITWISE(GPIOD_OUTPUT_VAL, 0x80); |
50 | set_irq_level(oldlevel); | 50 | restore_irq(oldlevel); |
51 | udelay(10); | 51 | udelay(10); |
52 | } | 52 | } |
53 | while (++current_dim < val); | 53 | while (++current_dim < val); |
@@ -56,11 +56,11 @@ void _backlight_set_brightness(int val) | |||
56 | { | 56 | { |
57 | do | 57 | do |
58 | { | 58 | { |
59 | oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL); | 59 | oldlevel = disable_irq_save(); |
60 | GPIO_CLEAR_BITWISE(GPIOD_OUTPUT_VAL, 0x80); | 60 | GPIO_CLEAR_BITWISE(GPIOD_OUTPUT_VAL, 0x80); |
61 | udelay(200); | 61 | udelay(200); |
62 | GPIO_SET_BITWISE(GPIOD_OUTPUT_VAL, 0x80); | 62 | GPIO_SET_BITWISE(GPIOD_OUTPUT_VAL, 0x80); |
63 | set_irq_level(oldlevel); | 63 | restore_irq(oldlevel); |
64 | udelay(10); | 64 | udelay(10); |
65 | } | 65 | } |
66 | while (--current_dim > val); | 66 | while (--current_dim > val); |
diff --git a/firmware/target/arm/ipod/video/lcd-video.c b/firmware/target/arm/ipod/video/lcd-video.c index d0c82e905c..0e1b072917 100644 --- a/firmware/target/arm/ipod/video/lcd-video.c +++ b/firmware/target/arm/ipod/video/lcd-video.c | |||
@@ -110,7 +110,7 @@ static void bcm_setup_rect(unsigned x, unsigned y, | |||
110 | #ifndef BOOTLOADER | 110 | #ifndef BOOTLOADER |
111 | static void lcd_tick(void) | 111 | static void lcd_tick(void) |
112 | { | 112 | { |
113 | /* No set_irq_level - already in interrupt context */ | 113 | /* No core level interrupt mask - already in interrupt context */ |
114 | #if NUM_CORES > 1 | 114 | #if NUM_CORES > 1 |
115 | corelock_lock(&lcd_state.cl); | 115 | corelock_lock(&lcd_state.cl); |
116 | #endif | 116 | #endif |
@@ -143,7 +143,7 @@ static void lcd_tick(void) | |||
143 | 143 | ||
144 | static inline void lcd_block_tick(void) | 144 | static inline void lcd_block_tick(void) |
145 | { | 145 | { |
146 | int oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL); | 146 | int oldlevel = disable_irq_save(); |
147 | 147 | ||
148 | #if NUM_CORES > 1 | 148 | #if NUM_CORES > 1 |
149 | corelock_lock(&lcd_state.cl); | 149 | corelock_lock(&lcd_state.cl); |
@@ -152,14 +152,14 @@ static inline void lcd_block_tick(void) | |||
152 | #else | 152 | #else |
153 | lcd_state.blocked = true; | 153 | lcd_state.blocked = true; |
154 | #endif | 154 | #endif |
155 | set_irq_level(oldlevel); | 155 | restore_irq(oldlevel); |
156 | } | 156 | } |
157 | 157 | ||
158 | static void lcd_unblock_and_update(void) | 158 | static void lcd_unblock_and_update(void) |
159 | { | 159 | { |
160 | unsigned data; | 160 | unsigned data; |
161 | bool bcm_is_busy; | 161 | bool bcm_is_busy; |
162 | int oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL); | 162 | int oldlevel = disable_irq_save(); |
163 | 163 | ||
164 | #if NUM_CORES > 1 | 164 | #if NUM_CORES > 1 |
165 | corelock_lock(&lcd_state.cl); | 165 | corelock_lock(&lcd_state.cl); |
@@ -184,7 +184,7 @@ static void lcd_unblock_and_update(void) | |||
184 | #if NUM_CORES > 1 | 184 | #if NUM_CORES > 1 |
185 | corelock_unlock(&lcd_state.cl); | 185 | corelock_unlock(&lcd_state.cl); |
186 | #endif | 186 | #endif |
187 | set_irq_level(oldlevel); | 187 | restore_irq(oldlevel); |
188 | } | 188 | } |
189 | 189 | ||
190 | #else /* BOOTLOADER */ | 190 | #else /* BOOTLOADER */ |
diff --git a/firmware/target/arm/pcm-pp.c b/firmware/target/arm/pcm-pp.c index 5a9d3b3670..433e6e1e4f 100644 --- a/firmware/target/arm/pcm-pp.c +++ b/firmware/target/arm/pcm-pp.c | |||
@@ -223,24 +223,24 @@ void fiq_playback(void) | |||
223 | will require other measures */ | 223 | will require other measures */ |
224 | void pcm_play_lock(void) | 224 | void pcm_play_lock(void) |
225 | { | 225 | { |
226 | int status = set_fiq_status(FIQ_DISABLED); | 226 | int status = disable_fiq_save(); |
227 | 227 | ||
228 | if (++dma_play_data.locked == 1) { | 228 | if (++dma_play_data.locked == 1) { |
229 | IIS_IRQTX_REG &= ~IIS_IRQTX; | 229 | IIS_IRQTX_REG &= ~IIS_IRQTX; |
230 | } | 230 | } |
231 | 231 | ||
232 | set_fiq_status(status); | 232 | restore_fiq(status); |
233 | } | 233 | } |
234 | 234 | ||
235 | void pcm_play_unlock(void) | 235 | void pcm_play_unlock(void) |
236 | { | 236 | { |
237 | int status = set_fiq_status(FIQ_DISABLED); | 237 | int status = disable_fiq_save(); |
238 | 238 | ||
239 | if (--dma_play_data.locked == 0 && dma_play_data.state != 0) { | 239 | if (--dma_play_data.locked == 0 && dma_play_data.state != 0) { |
240 | IIS_IRQTX_REG |= IIS_IRQTX; | 240 | IIS_IRQTX_REG |= IIS_IRQTX; |
241 | } | 241 | } |
242 | 242 | ||
243 | set_fiq_status(status); | 243 | restore_fiq(status); |
244 | } | 244 | } |
245 | 245 | ||
246 | static void play_start_pcm(void) | 246 | static void play_start_pcm(void) |
@@ -373,22 +373,22 @@ static struct dma_data dma_rec_data NOCACHEBSS_ATTR = | |||
373 | will require other measures */ | 373 | will require other measures */ |
374 | void pcm_rec_lock(void) | 374 | void pcm_rec_lock(void) |
375 | { | 375 | { |
376 | int status = set_fiq_status(FIQ_DISABLED); | 376 | int status = disable_fiq_save(); |
377 | 377 | ||
378 | if (++dma_rec_data.locked == 1) | 378 | if (++dma_rec_data.locked == 1) |
379 | IIS_IRQRX_REG &= ~IIS_IRQRX; | 379 | IIS_IRQRX_REG &= ~IIS_IRQRX; |
380 | 380 | ||
381 | set_fiq_status(status); | 381 | restore_fiq(status); |
382 | } | 382 | } |
383 | 383 | ||
384 | void pcm_rec_unlock(void) | 384 | void pcm_rec_unlock(void) |
385 | { | 385 | { |
386 | int status = set_fiq_status(FIQ_DISABLED); | 386 | int status = disable_fiq_save(); |
387 | 387 | ||
388 | if (--dma_rec_data.locked == 0 && dma_rec_data.state != 0) | 388 | if (--dma_rec_data.locked == 0 && dma_rec_data.state != 0) |
389 | IIS_IRQRX_REG |= IIS_IRQRX; | 389 | IIS_IRQRX_REG |= IIS_IRQRX; |
390 | 390 | ||
391 | set_fiq_status(status); | 391 | restore_fiq(status); |
392 | } | 392 | } |
393 | 393 | ||
394 | /* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */ | 394 | /* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */ |
diff --git a/firmware/target/arm/pnx0101/iriver-ifp7xx/power-ifp7xx.c b/firmware/target/arm/pnx0101/iriver-ifp7xx/power-ifp7xx.c index b219244510..4494742bb8 100644 --- a/firmware/target/arm/pnx0101/iriver-ifp7xx/power-ifp7xx.c +++ b/firmware/target/arm/pnx0101/iriver-ifp7xx/power-ifp7xx.c | |||
@@ -55,11 +55,10 @@ bool ide_powered(void) | |||
55 | 55 | ||
56 | void power_off(void) | 56 | void power_off(void) |
57 | { | 57 | { |
58 | set_irq_level(HIGHEST_IRQ_LEVEL); | 58 | disable_interrupt(IRQ_FIQ_STATUS); |
59 | GPIO1_CLR = 1 << 16; | 59 | GPIO1_CLR = 1 << 16; |
60 | GPIO2_SET = 1; | 60 | GPIO2_SET = 1; |
61 | while(1) | 61 | while(1); |
62 | yield(); | ||
63 | } | 62 | } |
64 | 63 | ||
65 | #else | 64 | #else |
diff --git a/firmware/target/arm/pnx0101/system-pnx0101.c b/firmware/target/arm/pnx0101/system-pnx0101.c index da94f397ca..bedcff04ea 100644 --- a/firmware/target/arm/pnx0101/system-pnx0101.c +++ b/firmware/target/arm/pnx0101/system-pnx0101.c | |||
@@ -113,7 +113,7 @@ static inline void *noncached(void *p) | |||
113 | static void do_set_mem_timings(void) ICODE_ATTR; | 113 | static void do_set_mem_timings(void) ICODE_ATTR; |
114 | static void do_set_mem_timings(void) | 114 | static void do_set_mem_timings(void) |
115 | { | 115 | { |
116 | int old_irq = set_irq_level(HIGHEST_IRQ_LEVEL); | 116 | int old_irq = disable_irq_save(); |
117 | while ((EMC.status & 3) != 0); | 117 | while ((EMC.status & 3) != 0); |
118 | EMC.control = 5; | 118 | EMC.control = 5; |
119 | EMCSTATIC0.waitrd = 6; | 119 | EMCSTATIC0.waitrd = 6; |
@@ -130,7 +130,7 @@ static void do_set_mem_timings(void) | |||
130 | EMCSTATIC1.config = 0x80081; | 130 | EMCSTATIC1.config = 0x80081; |
131 | #endif | 131 | #endif |
132 | EMC.control = 1; | 132 | EMC.control = 1; |
133 | set_irq_level(old_irq); | 133 | restore_irq(old_irq); |
134 | } | 134 | } |
135 | 135 | ||
136 | static void emc_set_mem_timings(void) | 136 | static void emc_set_mem_timings(void) |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c index 7f25cb6a15..00be543bb6 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | |||
@@ -66,27 +66,27 @@ static void _pcm_apply_settings(void) | |||
66 | 66 | ||
67 | void pcm_apply_settings(void) | 67 | void pcm_apply_settings(void) |
68 | { | 68 | { |
69 | int oldstatus = set_fiq_status(FIQ_DISABLED); | 69 | int status = disable_fiq_save(); |
70 | _pcm_apply_settings(); | 70 | _pcm_apply_settings(); |
71 | set_fiq_status(oldstatus); | 71 | restore_fiq(status); |
72 | } | 72 | } |
73 | 73 | ||
74 | /* For the locks, DMA interrupt must be disabled because the handler | 74 | /* For the locks, DMA interrupt must be disabled because the handler |
75 | manipulates INTMSK and the operation is not atomic */ | 75 | manipulates INTMSK and the operation is not atomic */ |
76 | void pcm_play_lock(void) | 76 | void pcm_play_lock(void) |
77 | { | 77 | { |
78 | int status = set_fiq_status(FIQ_DISABLED); | 78 | int status = disable_fiq_save(); |
79 | if (++dma_play_lock.locked == 1) | 79 | if (++dma_play_lock.locked == 1) |
80 | INTMSK |= (1<<19); /* Mask the DMA interrupt */ | 80 | INTMSK |= (1<<19); /* Mask the DMA interrupt */ |
81 | set_fiq_status(status); | 81 | restore_fiq(status); |
82 | } | 82 | } |
83 | 83 | ||
84 | void pcm_play_unlock(void) | 84 | void pcm_play_unlock(void) |
85 | { | 85 | { |
86 | int status = set_fiq_status(FIQ_DISABLED); | 86 | int status = disable_fiq_save(); |
87 | if (--dma_play_lock.locked == 0) | 87 | if (--dma_play_lock.locked == 0) |
88 | INTMSK &= ~dma_play_lock.state; /* Unmask the DMA interrupt if enabled */ | 88 | INTMSK &= ~dma_play_lock.state; /* Unmask the DMA interrupt if enabled */ |
89 | set_fiq_status(status); | 89 | restore_fiq(status); |
90 | } | 90 | } |
91 | 91 | ||
92 | void pcm_play_dma_init(void) | 92 | void pcm_play_dma_init(void) |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/timer-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/timer-meg-fx.c index 7df20f7149..b59e95806d 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/timer-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/timer-meg-fx.c | |||
@@ -66,7 +66,7 @@ bool __timer_set(long cycles, bool start) | |||
66 | pfn_unregister = NULL; | 66 | pfn_unregister = NULL; |
67 | } | 67 | } |
68 | 68 | ||
69 | oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL); | 69 | oldlevel = disable_irq_save(); |
70 | 70 | ||
71 | TCMPB0 = 0; | 71 | TCMPB0 = 0; |
72 | TCNTB0 = (unsigned int)cycles / prescaler; | 72 | TCNTB0 = (unsigned int)cycles / prescaler; |
@@ -77,7 +77,7 @@ bool __timer_set(long cycles, bool start) | |||
77 | TCFG0 = (TCFG0 & ~0xff) | (prescaler - 1); | 77 | TCFG0 = (TCFG0 & ~0xff) | (prescaler - 1); |
78 | TCFG1 = (TCFG1 & ~0xf) | divider; | 78 | TCFG1 = (TCFG1 & ~0xf) | divider; |
79 | 79 | ||
80 | set_irq_level(oldlevel); | 80 | restore_irq(oldlevel); |
81 | 81 | ||
82 | retval = true; | 82 | retval = true; |
83 | } | 83 | } |
diff --git a/firmware/target/arm/system-arm.h b/firmware/target/arm/system-arm.h index 774cdbcff4..3f1dfb16c8 100644 --- a/firmware/target/arm/system-arm.h +++ b/firmware/target/arm/system-arm.h | |||
@@ -74,27 +74,7 @@ static inline uint32_t swap_odd_even32(uint32_t value) | |||
74 | return value; | 74 | return value; |
75 | } | 75 | } |
76 | 76 | ||
77 | static inline void enable_fiq(void) | 77 | /* Core-level interrupt masking */ |
78 | { | ||
79 | /* Clear FIQ disable bit */ | ||
80 | asm volatile ( | ||
81 | "mrs r0, cpsr \n"\ | ||
82 | "bic r0, r0, #0x40 \n"\ | ||
83 | "msr cpsr_c, r0 " | ||
84 | : : : "r0" | ||
85 | ); | ||
86 | } | ||
87 | |||
88 | static inline void disable_fiq(void) | ||
89 | { | ||
90 | /* Set FIQ disable bit */ | ||
91 | asm volatile ( | ||
92 | "mrs r0, cpsr \n"\ | ||
93 | "orr r0, r0, #0x40 \n"\ | ||
94 | "msr cpsr_c, r0 " | ||
95 | : : : "r0" | ||
96 | ); | ||
97 | } | ||
98 | 78 | ||
99 | /* This one returns the old status */ | 79 | /* This one returns the old status */ |
100 | #define IRQ_ENABLED 0x00 | 80 | #define IRQ_ENABLED 0x00 |
@@ -108,8 +88,10 @@ static inline void disable_fiq(void) | |||
108 | #define IRQ_FIQ_STATUS 0xc0 | 88 | #define IRQ_FIQ_STATUS 0xc0 |
109 | #define HIGHEST_IRQ_LEVEL IRQ_DISABLED | 89 | #define HIGHEST_IRQ_LEVEL IRQ_DISABLED |
110 | 90 | ||
111 | #define set_irq_level(status) set_interrupt_status((status), IRQ_STATUS) | 91 | #define set_irq_level(status) \ |
112 | #define set_fiq_status(status) set_interrupt_status((status), FIQ_STATUS) | 92 | set_interrupt_status((status), IRQ_STATUS) |
93 | #define set_fiq_status(status) \ | ||
94 | set_interrupt_status((status), FIQ_STATUS) | ||
113 | 95 | ||
114 | static inline int set_interrupt_status(int status, int mask) | 96 | static inline int set_interrupt_status(int status, int mask) |
115 | { | 97 | { |
@@ -122,10 +104,75 @@ static inline int set_interrupt_status(int status, int mask) | |||
122 | "orr %0, %0, %2 \n" | 104 | "orr %0, %0, %2 \n" |
123 | "msr cpsr_c, %0 \n" | 105 | "msr cpsr_c, %0 \n" |
124 | : "=&r,r"(cpsr), "=&r,r"(oldstatus) | 106 | : "=&r,r"(cpsr), "=&r,r"(oldstatus) |
125 | : "r,i"(status & mask), [mask]"i,i"(mask) | 107 | : "r,i"(status & mask), [mask]"i,i"(mask)); |
126 | ); | ||
127 | 108 | ||
128 | return oldstatus; | 109 | return oldstatus; |
129 | } | 110 | } |
130 | 111 | ||
112 | static inline void enable_interrupt(int mask) | ||
113 | { | ||
114 | /* Clear I and/or F disable bit */ | ||
115 | int tmp; | ||
116 | asm volatile ( | ||
117 | "mrs %0, cpsr \n" | ||
118 | "bic %0, %0, %1 \n" | ||
119 | "msr cpsr_c, %0 \n" | ||
120 | : "=&r"(tmp) : "i"(mask)); | ||
121 | } | ||
122 | |||
123 | static inline void disable_interrupt(int mask) | ||
124 | { | ||
125 | /* Set I and/or F disable bit */ | ||
126 | int tmp; | ||
127 | asm volatile ( | ||
128 | "mrs %0, cpsr \n" | ||
129 | "orr %0, %0, %1 \n" | ||
130 | "msr cpsr_c, %0 \n" | ||
131 | : "=&r"(tmp) : "i"(mask)); | ||
132 | } | ||
133 | |||
134 | #define disable_irq(void) \ | ||
135 | disable_interrupt(IRQ_STATUS) | ||
136 | |||
137 | #define enable_irq(void) \ | ||
138 | enable_interrupt(IRQ_STATUS) | ||
139 | |||
140 | #define disable_fiq(void) \ | ||
141 | disable_interrupt(FIQ_STATUS) | ||
142 | |||
143 | #define enable_fiq(void) \ | ||
144 | enable_interrupt(FIQ_STATUS) | ||
145 | |||
146 | static inline int disable_interrupt_save(int mask) | ||
147 | { | ||
148 | /* Set I and/or F disable bit and return old cpsr value */ | ||
149 | int cpsr, tmp; | ||
150 | asm volatile ( | ||
151 | "mrs %1, cpsr \n" | ||
152 | "orr %0, %1, %2 \n" | ||
153 | "msr cpsr_c, %0 \n" | ||
154 | : "=&r"(tmp), "=&r"(cpsr) | ||
155 | : "i"(mask)); | ||
156 | return cpsr; | ||
157 | } | ||
158 | |||
159 | #define disable_irq_save() \ | ||
160 | disable_interrupt_save(IRQ_STATUS) | ||
161 | |||
162 | #define disable_fiq_save() \ | ||
163 | disable_interrupt_save(FIQ_STATUS) | ||
164 | |||
165 | static inline void restore_interrupt(int cpsr) | ||
166 | { | ||
167 | /* Set cpsr_c from value returned by disable_interrupt_save | ||
168 | * or set_interrupt_status */ | ||
169 | asm volatile ("msr cpsr_c, %0" : : "r"(cpsr)); | ||
170 | } | ||
171 | |||
172 | #define restore_irq(cpsr) \ | ||
173 | restore_interrupt(cpsr) | ||
174 | |||
175 | #define restore_fiq(cpsr) \ | ||
176 | restore_interrupt(cpsr) | ||
177 | |||
131 | #endif /* SYSTEM_ARM_H */ | 178 | #endif /* SYSTEM_ARM_H */ |
diff --git a/firmware/target/arm/tatung/tpj1022/backlight-tpj1022.c b/firmware/target/arm/tatung/tpj1022/backlight-tpj1022.c index 933ad5e930..a466cd93dd 100644 --- a/firmware/target/arm/tatung/tpj1022/backlight-tpj1022.c +++ b/firmware/target/arm/tatung/tpj1022/backlight-tpj1022.c | |||
@@ -28,17 +28,17 @@ | |||
28 | void _backlight_on(void) | 28 | void _backlight_on(void) |
29 | { | 29 | { |
30 | #if 0 | 30 | #if 0 |
31 | int level = set_irq_level(HIGHEST_IRQ_LEVEL); | 31 | int level = disable_irq_save(); |
32 | pcf50606_write(0x38, 0xb0); /* Backlight ON, GPO1INV=1, GPO1ACT=011 */ | 32 | pcf50606_write(0x38, 0xb0); /* Backlight ON, GPO1INV=1, GPO1ACT=011 */ |
33 | set_irq_level(level); | 33 | restore_irq(level); |
34 | #endif | 34 | #endif |
35 | } | 35 | } |
36 | 36 | ||
37 | void _backlight_off(void) | 37 | void _backlight_off(void) |
38 | { | 38 | { |
39 | #if 0 | 39 | #if 0 |
40 | int level = set_irq_level(HIGHEST_IRQ_LEVEL); | 40 | int level = disable_irq_save(); |
41 | pcf50606_write(0x38, 0x80); /* Backlight OFF, GPO1INV=1, GPO1ACT=000 */ | 41 | pcf50606_write(0x38, 0x80); /* Backlight OFF, GPO1INV=1, GPO1ACT=000 */ |
42 | set_irq_level(level); | 42 | restore_irq(level); |
43 | #endif | 43 | #endif |
44 | } | 44 | } |
diff --git a/firmware/target/arm/tms320dm320/dsp-dm320.c b/firmware/target/arm/tms320dm320/dsp-dm320.c index f2ca954b24..e082cf7e4d 100644 --- a/firmware/target/arm/tms320dm320/dsp-dm320.c +++ b/firmware/target/arm/tms320dm320/dsp-dm320.c | |||
@@ -85,7 +85,7 @@ void dsp_wake(void) | |||
85 | { | 85 | { |
86 | /* If this is called concurrently, we may overlap setting and resetting the | 86 | /* If this is called concurrently, we may overlap setting and resetting the |
87 | bit, which causes lost interrupts to the DSP. */ | 87 | bit, which causes lost interrupts to the DSP. */ |
88 | int old_level = set_irq_level(IRQ_DISABLED); | 88 | int old_level = disable_irq_save(); |
89 | 89 | ||
90 | /* The first time you INT0 the DSP, the ROM loader will branch to your RST | 90 | /* The first time you INT0 the DSP, the ROM loader will branch to your RST |
91 | handler. Subsequent times, your INT0 handler will get executed. */ | 91 | handler. Subsequent times, your INT0 handler will get executed. */ |
@@ -93,7 +93,7 @@ void dsp_wake(void) | |||
93 | nop; nop; | 93 | nop; nop; |
94 | IO_DSPC_HPIB_CONTROL |= 1 << 7; | 94 | IO_DSPC_HPIB_CONTROL |= 1 << 7; |
95 | 95 | ||
96 | set_irq_level(old_level); | 96 | restore_irq(old_level); |
97 | } | 97 | } |
98 | 98 | ||
99 | static void dsp_load(const struct dsp_section *im) | 99 | static void dsp_load(const struct dsp_section *im) |
diff --git a/firmware/target/arm/tms320dm320/timer-dm320.c b/firmware/target/arm/tms320dm320/timer-dm320.c index 482fef9f12..e1e051d3a5 100644 --- a/firmware/target/arm/tms320dm320/timer-dm320.c +++ b/firmware/target/arm/tms320dm320/timer-dm320.c | |||
@@ -48,7 +48,7 @@ bool __timer_set(long cycles, bool start) | |||
48 | pfn_unregister = NULL; | 48 | pfn_unregister = NULL; |
49 | } | 49 | } |
50 | 50 | ||
51 | oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL); | 51 | oldlevel = disable_irq_save(); |
52 | 52 | ||
53 | /* Increase prescale values starting from 0 to make the cycle count fit */ | 53 | /* Increase prescale values starting from 0 to make the cycle count fit */ |
54 | while(divider>65535 && prescaler<1024) | 54 | while(divider>65535 && prescaler<1024) |
@@ -60,7 +60,7 @@ bool __timer_set(long cycles, bool start) | |||
60 | IO_TIMER0_TMPRSCL = prescaler; | 60 | IO_TIMER0_TMPRSCL = prescaler; |
61 | IO_TIMER0_TMDIV = divider; | 61 | IO_TIMER0_TMDIV = divider; |
62 | 62 | ||
63 | set_irq_level(oldlevel); | 63 | restore_irq(oldlevel); |
64 | 64 | ||
65 | return true; | 65 | return true; |
66 | } | 66 | } |