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-rw-r--r--firmware/target/arm/as3525/clock-target.h35
1 files changed, 28 insertions, 7 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index 7f6b17eff4..2f2f90b24f 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -158,22 +158,38 @@
158#endif /* CONFIG_CPU */ 158#endif /* CONFIG_CPU */
159 159
160 /* PCLK as Source */ 160 /* PCLK as Source */
161 #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ 161 #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
162 #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) 162
163 #define AS3525_I2C_FREQ 400000 163 #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */
164 #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) 164#if LCD_DEPTH > 1
165 #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ 165 #define AS3525_SSP_PRESCALER_MAX ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ_MIN) + 1) & ~1)/* must be an even number */
166 #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */ 166 #define AS3525_SSP_FREQ_MIN 2000000 /* 2 MHz gives a decent refresh rate on clipzip*/
167 #define AS3525_SSP_FREQ 12000000 167#else
168 #define AS3525_SSP_PRESCALER_MAX 0xFE & ~1 /*Max value for divider - must be an even number */
169 #define AS3525_SSP_FREQ_MIN AS3525_SSP_FREQ /* No set minimum we just use max divider */
170#endif
171 #define AS3525_SSP_FREQ 12000000
172
173 #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
174 #define AS3525_I2C_PRESCALER_MAX 0xFF | 0x300 /* Max value for prescaler */
175 #define AS3525_I2C_FREQ 400000
176
177 #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
178 #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
179
168 180
169#define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ 181#define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */
170#define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ 182#define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
183#define AS3525_IDE_DIV_MAX 0xF /* Max value for divider */
171 184
172#if CONFIG_CPU == AS3525v2 185#if CONFIG_CPU == AS3525v2
173#define AS3525_MS_FREQ 120000000 186#define AS3525_MS_FREQ 120000000
174#define AS3525_MS_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) 187#define AS3525_MS_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1)
188
175#define AS3525_SDSLOT_FREQ 24000000 189#define AS3525_SDSLOT_FREQ 24000000
176#define AS3525_SDSLOT_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_SDSLOT_FREQ) -1) 190#define AS3525_SDSLOT_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_SDSLOT_FREQ) -1)
191#define AS3525_SDSLOT_DIV_MAX 0xF /* Max value for divider */
192
177#define AS3525_IDE_FREQ 80000000 193#define AS3525_IDE_FREQ 80000000
178#else 194#else
179#define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */ 195#define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */
@@ -211,6 +227,10 @@
211#error SSP frequency is too low : clock divider will not fit ! 227#error SSP frequency is too low : clock divider will not fit !
212#endif 228#endif
213 229
230#if (((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ_MIN)) + 1 ) & ~1) >= (1<<8) /* 8 bits */
231#error SSP_MIN frequency is too low : clock divider will not fit !
232#endif
233
214/* AS3525_SD_IDENT_FREQ */ 234/* AS3525_SD_IDENT_FREQ */
215#if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ 235#if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */
216#error SD IDENTIFICATION frequency is too low : clock divider will not fit ! 236#error SD IDENTIFICATION frequency is too low : clock divider will not fit !
@@ -227,3 +247,4 @@
227#endif 247#endif
228 248
229#endif /* CLOCK_TARGET_H */ 249#endif /* CLOCK_TARGET_H */
250