diff options
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/s5l8700/crt0.S | 108 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/mmu-s5l8700.S | 190 |
2 files changed, 149 insertions, 149 deletions
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S index bb6d910e22..583b762505 100644 --- a/firmware/target/arm/s5l8700/crt0.S +++ b/firmware/target/arm/s5l8700/crt0.S | |||
@@ -260,64 +260,64 @@ start_loc: | |||
260 | 260 | ||
261 | #if defined(MEIZU_M6SP) || defined(MEIZU_M3) | 261 | #if defined(MEIZU_M6SP) || defined(MEIZU_M3) |
262 | /* setup SDRAM for Meizu M6SP */ | 262 | /* setup SDRAM for Meizu M6SP */ |
263 | ldr r1, =0x38200000 | 263 | ldr r1, =0x38200000 |
264 | // configure SDR drive strength and pad settings | 264 | // configure SDR drive strength and pad settings |
265 | mov r0, #SDR_DSS_SEL_B | 265 | mov r0, #SDR_DSS_SEL_B |
266 | str r0, [r1, #0x4C] // MIU_DSS_SEL_B | 266 | str r0, [r1, #0x4C] // MIU_DSS_SEL_B |
267 | mov r0, #SDR_DSS_SEL_O | 267 | mov r0, #SDR_DSS_SEL_O |
268 | str r0, [r1, #0x50] // MIU_DSS_SEL_O | 268 | str r0, [r1, #0x50] // MIU_DSS_SEL_O |
269 | mov r0, #SDR_DSS_SEL_C | 269 | mov r0, #SDR_DSS_SEL_C |
270 | str r0, [r1, #0x54] // MIU_DSS_SEL_C | 270 | str r0, [r1, #0x54] // MIU_DSS_SEL_C |
271 | mov r0, #2 | 271 | mov r0, #2 |
272 | str r0, [r1, #0x60] // SSTL2_PAD_ON | 272 | str r0, [r1, #0x60] // SSTL2_PAD_ON |
273 | // select SDR mode | 273 | // select SDR mode |
274 | ldr r0, [r1, #0x40] | 274 | ldr r0, [r1, #0x40] |
275 | mov r2, #0xFFFDFFFF | 275 | mov r2, #0xFFFDFFFF |
276 | and r0, r0, r2 | 276 | and r0, r0, r2 |
277 | orr r0, r0, #1 | 277 | orr r0, r0, #1 |
278 | str r0, [r1, #0x40] // MIUORG | 278 | str r0, [r1, #0x40] // MIUORG |
279 | // set controller configuration | 279 | // set controller configuration |
280 | mov r0, #SDR_CONFIG | 280 | mov r0, #SDR_CONFIG |
281 | str r0, [r1] // MIUCON | 281 | str r0, [r1] // MIUCON |
282 | // set SDRAM timing | 282 | // set SDRAM timing |
283 | ldr r0, =SDR_TIMING | 283 | ldr r0, =SDR_TIMING |
284 | str r0, [r1, #0x10] // MIUSDPARA | 284 | str r0, [r1, #0x10] // MIUSDPARA |
285 | // set refresh rate | 285 | // set refresh rate |
286 | mov r0, #0x1080 | 286 | mov r0, #0x1080 |
287 | str r0, [r1, #0x08] // MIUAREF | 287 | str r0, [r1, #0x08] // MIUAREF |
288 | // initialise SDRAM | 288 | // initialise SDRAM |
289 | mov r0, #0x003 | 289 | mov r0, #0x003 |
290 | str r0, [r1, #0x04] // MIUCOM = nop | 290 | str r0, [r1, #0x04] // MIUCOM = nop |
291 | ldr r0, =0x203 | 291 | ldr r0, =0x203 |
292 | str r0, [r1, #0x04] // MIUCOM = precharge all banks | 292 | str r0, [r1, #0x04] // MIUCOM = precharge all banks |
293 | nop | 293 | nop |
294 | nop | 294 | nop |
295 | nop | 295 | nop |
296 | ldr r0, =0x303 | 296 | ldr r0, =0x303 |
297 | str r0, [r1, #0x04] // MIUCOM = auto-refresh | 297 | str r0, [r1, #0x04] // MIUCOM = auto-refresh |
298 | nop | 298 | nop |
299 | nop | 299 | nop |
300 | nop | 300 | nop |
301 | nop | 301 | nop |
302 | str r0, [r1, #0x04] // MIUCOM = auto-refresh | 302 | str r0, [r1, #0x04] // MIUCOM = auto-refresh |
303 | nop | 303 | nop |
304 | nop | 304 | nop |
305 | nop | 305 | nop |
306 | nop | 306 | nop |
307 | str r0, [r1, #0x04] // MIUCOM = auto-refresh | 307 | str r0, [r1, #0x04] // MIUCOM = auto-refresh |
308 | nop | 308 | nop |
309 | nop | 309 | nop |
310 | nop | 310 | nop |
311 | nop | 311 | nop |
312 | // set mode register | 312 | // set mode register |
313 | mov r0, #SDR_MRS | 313 | mov r0, #SDR_MRS |
314 | str r0, [r1, #0x0C] // MIUMRS | 314 | str r0, [r1, #0x0C] // MIUMRS |
315 | ldr r0, =0x103 | 315 | ldr r0, =0x103 |
316 | str r0, [r1, #0x04] // MIUCOM = mode register set | 316 | str r0, [r1, #0x04] // MIUCOM = mode register set |
317 | ldr r0, =SDR_EMRS | 317 | ldr r0, =SDR_EMRS |
318 | str r0, [r1, #0x0C] // MIUMRS | 318 | str r0, [r1, #0x0C] // MIUMRS |
319 | ldr r0, =0x103 | 319 | ldr r0, =0x103 |
320 | str r0, [r1, #0x04] // MIUCOM = mode register set | 320 | str r0, [r1, #0x04] // MIUCOM = mode register set |
321 | #endif /* MEIZU_M6SP */ | 321 | #endif /* MEIZU_M6SP */ |
322 | 322 | ||
323 | mov r1, #0x1 | 323 | mov r1, #0x1 |
diff --git a/firmware/target/arm/s5l8700/mmu-s5l8700.S b/firmware/target/arm/s5l8700/mmu-s5l8700.S index f2795d56eb..b745c8bb04 100644 --- a/firmware/target/arm/s5l8700/mmu-s5l8700.S +++ b/firmware/target/arm/s5l8700/mmu-s5l8700.S | |||
@@ -1,95 +1,95 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id$ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2006,2007 by Greg White | 10 | * Copyright (C) 2006,2007 by Greg White |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | #include "config.h" | 21 | #include "config.h" |
22 | #include "cpu.h" | 22 | #include "cpu.h" |
23 | 23 | ||
24 | /** Cache coherency **/ | 24 | /** Cache coherency **/ |
25 | 25 | ||
26 | /* | 26 | /* |
27 | * Cleans entire DCache | 27 | * Cleans entire DCache |
28 | * void clean_dcache(void); | 28 | * void clean_dcache(void); |
29 | */ | 29 | */ |
30 | .section .icode, "ax", %progbits | 30 | .section .icode, "ax", %progbits |
31 | .align 2 | 31 | .align 2 |
32 | .global clean_dcache | 32 | .global clean_dcache |
33 | .type clean_dcache, %function | 33 | .type clean_dcache, %function |
34 | .global cpucache_flush @ Alias | 34 | .global cpucache_flush @ Alias |
35 | clean_dcache: | 35 | clean_dcache: |
36 | cpucache_flush: | 36 | cpucache_flush: |
37 | @ Index format: 31:26 = index, 7:5 = segment, remainder = SBZ | 37 | @ Index format: 31:26 = index, 7:5 = segment, remainder = SBZ |
38 | mov r1, #0x00000000 @ | 38 | mov r1, #0x00000000 @ |
39 | 1: @ clean_start @ | 39 | 1: @ clean_start @ |
40 | mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index | 40 | mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index |
41 | add r0, r1, #0x00000010 @ | 41 | add r0, r1, #0x00000010 @ |
42 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | 42 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index |
43 | add r0, r0, #0x00000010 @ | 43 | add r0, r0, #0x00000010 @ |
44 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | 44 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index |
45 | add r0, r0, #0x00000010 @ | 45 | add r0, r0, #0x00000010 @ |
46 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | 46 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index |
47 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end | 47 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end |
48 | bne 1b @ clean_start @ | 48 | bne 1b @ clean_start @ |
49 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer | 49 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer |
50 | bx lr @ | 50 | bx lr @ |
51 | .size clean_dcache, .-clean_dcache | 51 | .size clean_dcache, .-clean_dcache |
52 | 52 | ||
53 | /* | 53 | /* |
54 | * Invalidate entire DCache | 54 | * Invalidate entire DCache |
55 | * will do writeback | 55 | * will do writeback |
56 | * void invalidate_dcache(void); | 56 | * void invalidate_dcache(void); |
57 | */ | 57 | */ |
58 | .section .icode, "ax", %progbits | 58 | .section .icode, "ax", %progbits |
59 | .align 2 | 59 | .align 2 |
60 | .global invalidate_dcache | 60 | .global invalidate_dcache |
61 | .type invalidate_dcache, %function | 61 | .type invalidate_dcache, %function |
62 | invalidate_dcache: | 62 | invalidate_dcache: |
63 | @ Index format: 31:26 = index, 7:5 = segment, remainder = SBZ | 63 | @ Index format: 31:26 = index, 7:5 = segment, remainder = SBZ |
64 | mov r1, #0x00000000 @ | 64 | mov r1, #0x00000000 @ |
65 | 1: @ inv_start @ | 65 | 1: @ inv_start @ |
66 | mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index | 66 | mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index |
67 | add r0, r1, #0x00000010 @ | 67 | add r0, r1, #0x00000010 @ |
68 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index | 68 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index |
69 | add r0, r0, #0x00000010 @ | 69 | add r0, r0, #0x00000010 @ |
70 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index | 70 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index |
71 | add r0, r0, #0x00000010 @ | 71 | add r0, r0, #0x00000010 @ |
72 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index | 72 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index |
73 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end | 73 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end |
74 | bne 1b @ inv_start @ | 74 | bne 1b @ inv_start @ |
75 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer | 75 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer |
76 | bx lr @ | 76 | bx lr @ |
77 | .size invalidate_dcache, .-invalidate_dcache | 77 | .size invalidate_dcache, .-invalidate_dcache |
78 | 78 | ||
79 | /* | 79 | /* |
80 | * Invalidate entire ICache and DCache | 80 | * Invalidate entire ICache and DCache |
81 | * will do writeback | 81 | * will do writeback |
82 | * void invalidate_idcache(void); | 82 | * void invalidate_idcache(void); |
83 | */ | 83 | */ |
84 | .section .icode, "ax", %progbits | 84 | .section .icode, "ax", %progbits |
85 | .align 2 | 85 | .align 2 |
86 | .global invalidate_idcache | 86 | .global invalidate_idcache |
87 | .type invalidate_idcache, %function | 87 | .type invalidate_idcache, %function |
88 | .global cpucache_invalidate @ Alias | 88 | .global cpucache_invalidate @ Alias |
89 | invalidate_idcache: | 89 | invalidate_idcache: |
90 | cpucache_invalidate: | 90 | cpucache_invalidate: |
91 | mov r2, lr @ save lr to r2, call uses r0 and r1 only | 91 | mov r2, lr @ save lr to r2, call uses r0 and r1 only |
92 | bl invalidate_dcache @ Clean and invalidate entire DCache | 92 | bl invalidate_dcache @ Clean and invalidate entire DCache |
93 | mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call) | 93 | mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call) |
94 | mov pc, r2 @ | 94 | mov pc, r2 @ |
95 | .size invalidate_idcache, .-invalidate_idcache | 95 | .size invalidate_idcache, .-invalidate_idcache |