diff options
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/ipod/button-clickwheel.c | 42 | ||||
-rw-r--r-- | firmware/target/arm/usb-s3c6400x.c | 43 |
2 files changed, 56 insertions, 29 deletions
diff --git a/firmware/target/arm/ipod/button-clickwheel.c b/firmware/target/arm/ipod/button-clickwheel.c index 580f95a453..4dfa4c0a6b 100644 --- a/firmware/target/arm/ipod/button-clickwheel.c +++ b/firmware/target/arm/ipod/button-clickwheel.c | |||
@@ -39,7 +39,7 @@ | |||
39 | #include "serial.h" | 39 | #include "serial.h" |
40 | #include "power.h" | 40 | #include "power.h" |
41 | #include "powermgmt.h" | 41 | #include "powermgmt.h" |
42 | #if defined(IPOD_NANO2G) | 42 | #if defined(IPOD_NANO2G) || defined(IPOD_6G) |
43 | #include "pmu-target.h" | 43 | #include "pmu-target.h" |
44 | #endif | 44 | #endif |
45 | 45 | ||
@@ -49,18 +49,8 @@ | |||
49 | 49 | ||
50 | #ifdef CPU_PP | 50 | #ifdef CPU_PP |
51 | #define CLICKWHEEL_DATA (*(volatile unsigned long*)(0x7000c140)) | 51 | #define CLICKWHEEL_DATA (*(volatile unsigned long*)(0x7000c140)) |
52 | #elif CONFIG_CPU==S5L8701 | 52 | #elif CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 |
53 | #define PCON15 (*((volatile uint32_t*)(0x3CF000F0))) | 53 | #define CLICKWHEEL_DATA WHEELRX |
54 | #define PUNK15 (*((volatile uint32_t*)(0x3CF000FC))) | ||
55 | #define WHEEL00 (*((volatile uint32_t*)(0x3C200000))) | ||
56 | #define WHEEL04 (*((volatile uint32_t*)(0x3C200004))) | ||
57 | #define WHEEL08 (*((volatile uint32_t*)(0x3C200008))) | ||
58 | #define WHEEL0C (*((volatile uint32_t*)(0x3C20000C))) | ||
59 | #define WHEEL10 (*((volatile uint32_t*)(0x3C200010))) | ||
60 | #define WHEELINT (*((volatile uint32_t*)(0x3C200014))) | ||
61 | #define WHEELRX (*((volatile uint32_t*)(0x3C200018))) | ||
62 | #define WHEELTX (*((volatile uint32_t*)(0x3C20001C))) | ||
63 | #define CLICKWHEEL_DATA (*(volatile unsigned long*)(0x3c200018)) | ||
64 | #else | 54 | #else |
65 | #error CPU architecture not supported! | 55 | #error CPU architecture not supported! |
66 | #endif | 56 | #endif |
@@ -93,7 +83,7 @@ int int_btn = BUTTON_NONE; | |||
93 | static bool send_events = true; | 83 | static bool send_events = true; |
94 | #endif | 84 | #endif |
95 | 85 | ||
96 | #if CONFIG_CPU==S5L8701 | 86 | #if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 |
97 | static struct wakeup button_init_wakeup; | 87 | static struct wakeup button_init_wakeup; |
98 | #endif | 88 | #endif |
99 | 89 | ||
@@ -265,7 +255,7 @@ static inline int ipod_4g_button_read(void) | |||
265 | } | 255 | } |
266 | 256 | ||
267 | } | 257 | } |
268 | #if CONFIG_CPU==S5L8701 | 258 | #if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 |
269 | else if ((status & 0x8000FFFF) == 0x8000023A) | 259 | else if ((status & 0x8000FFFF) == 0x8000023A) |
270 | { | 260 | { |
271 | if (status & 0x00010000) | 261 | if (status & 0x00010000) |
@@ -345,7 +335,7 @@ bool headphones_inserted(void) | |||
345 | return (GPIOA_INPUT_VAL & 0x80)?true:false; | 335 | return (GPIOA_INPUT_VAL & 0x80)?true:false; |
346 | } | 336 | } |
347 | #else | 337 | #else |
348 | void INT_SPI(void) | 338 | void INT_WHEEL(void) |
349 | { | 339 | { |
350 | int clickwheel_events = WHEELINT; | 340 | int clickwheel_events = WHEELINT; |
351 | 341 | ||
@@ -359,6 +349,7 @@ void INT_SPI(void) | |||
359 | 349 | ||
360 | void s5l_clickwheel_init(void) | 350 | void s5l_clickwheel_init(void) |
361 | { | 351 | { |
352 | #if CONFIG_CPU==S5L8701 | ||
362 | PWRCONEXT &= ~1; | 353 | PWRCONEXT &= ~1; |
363 | PCON15 = (PCON15 & ~0xFFFF0000) | 0x22220000; | 354 | PCON15 = (PCON15 & ~0xFFFF0000) | 0x22220000; |
364 | PUNK15 = 0xF0; | 355 | PUNK15 = 0xF0; |
@@ -370,24 +361,35 @@ void s5l_clickwheel_init(void) | |||
370 | WHEELTX = 0x8000023A; | 361 | WHEELTX = 0x8000023A; |
371 | WHEEL04 |= 1; | 362 | WHEEL04 |= 1; |
372 | PDAT10 &= ~2; | 363 | PDAT10 &= ~2; |
364 | #elif CONFIG_CPU==S5L8702 | ||
365 | //TODO: Implement | ||
366 | #endif | ||
373 | } | 367 | } |
374 | 368 | ||
375 | void button_init_device(void) | 369 | void button_init_device(void) |
376 | { | 370 | { |
377 | wakeup_init(&button_init_wakeup); | 371 | wakeup_init(&button_init_wakeup); |
372 | #if CONFIG_CPU==S5L8701 | ||
378 | INTMSK |= (1<<26); | 373 | INTMSK |= (1<<26); |
374 | #elif CONFIG_CPU==S5L8702 | ||
375 | //TODO: Implement | ||
376 | #endif | ||
379 | s5l_clickwheel_init(); | 377 | s5l_clickwheel_init(); |
380 | wakeup_wait(&button_init_wakeup, HZ / 10); | 378 | wakeup_wait(&button_init_wakeup, HZ / 10); |
381 | } | 379 | } |
382 | 380 | ||
383 | bool button_hold(void) | 381 | bool button_hold(void) |
384 | { | 382 | { |
385 | return ((PDAT14 & (1 << 6)) == 0); | 383 | //TODO: Implement |
384 | //return ((PDAT14 & (1 << 6)) == 0); | ||
385 | return false; | ||
386 | } | 386 | } |
387 | 387 | ||
388 | bool headphones_inserted(void) | 388 | bool headphones_inserted(void) |
389 | { | 389 | { |
390 | return ((PDAT14 & (1 << 5)) != 0); | 390 | //TODO: Implement |
391 | //return ((PDAT14 & (1 << 5)) == 0); | ||
392 | return false; | ||
391 | } | 393 | } |
392 | #endif | 394 | #endif |
393 | 395 | ||
@@ -419,6 +421,8 @@ int button_read_device(void) | |||
419 | WHEEL00 = 0; | 421 | WHEEL00 = 0; |
420 | WHEEL10 = 0; | 422 | WHEEL10 = 0; |
421 | PWRCONEXT |= 1; | 423 | PWRCONEXT |= 1; |
424 | #elif CONFIG_CPU==S5L8702 | ||
425 | //TODO: Implement | ||
422 | #endif | 426 | #endif |
423 | } | 427 | } |
424 | else | 428 | else |
@@ -430,6 +434,8 @@ int button_read_device(void) | |||
430 | #elif CONFIG_CPU==S5L8701 | 434 | #elif CONFIG_CPU==S5L8701 |
431 | pmu_ldo_power_on(1); /* enable clickwheel power supply */ | 435 | pmu_ldo_power_on(1); /* enable clickwheel power supply */ |
432 | s5l_clickwheel_init(); | 436 | s5l_clickwheel_init(); |
437 | #elif CONFIG_CPU==S5L8702 | ||
438 | //TODO: Implement | ||
433 | #endif | 439 | #endif |
434 | } | 440 | } |
435 | } | 441 | } |
diff --git a/firmware/target/arm/usb-s3c6400x.c b/firmware/target/arm/usb-s3c6400x.c index e94c54f086..ba3b69a02e 100644 --- a/firmware/target/arm/usb-s3c6400x.c +++ b/firmware/target/arm/usb-s3c6400x.c | |||
@@ -24,15 +24,13 @@ | |||
24 | #include "usb-target.h" | 24 | #include "usb-target.h" |
25 | #include "usb_drv.h" | 25 | #include "usb_drv.h" |
26 | 26 | ||
27 | #define OTGBASE 0x38800000 | ||
28 | #define PHYBASE 0x3C400000 | ||
29 | #include "usb-s3c6400x.h" | ||
30 | |||
31 | #include "cpu.h" | 27 | #include "cpu.h" |
32 | #include "system.h" | 28 | #include "system.h" |
33 | #include "kernel.h" | 29 | #include "kernel.h" |
34 | #include "panic.h" | 30 | #include "panic.h" |
35 | 31 | ||
32 | #include "usb-s3c6400x.h" | ||
33 | |||
36 | #ifdef HAVE_USBSTACK | 34 | #ifdef HAVE_USBSTACK |
37 | #include "usb_ch9.h" | 35 | #include "usb_ch9.h" |
38 | #include "usb_core.h" | 36 | #include "usb_core.h" |
@@ -72,7 +70,7 @@ static void reset_endpoints(int reinit) | |||
72 | DOEPCTL0 = 0x8000; /* EP0 OUT ACTIVE */ | 70 | DOEPCTL0 = 0x8000; /* EP0 OUT ACTIVE */ |
73 | DOEPTSIZ0 = 0x20080040; /* EP0 OUT Transfer Size: | 71 | DOEPTSIZ0 = 0x20080040; /* EP0 OUT Transfer Size: |
74 | 64 Bytes, 1 Packet, 1 Setup Packet */ | 72 | 64 Bytes, 1 Packet, 1 Setup Packet */ |
75 | DOEPDMA0 = (uint32_t)&ctrlreq; | 73 | DOEPDMA0 = &ctrlreq; |
76 | DOEPCTL0 |= 0x84000000; /* EP0 OUT ENABLE CLEARNAK */ | 74 | DOEPCTL0 |= 0x84000000; /* EP0 OUT ENABLE CLEARNAK */ |
77 | if (reinit) | 75 | if (reinit) |
78 | { | 76 | { |
@@ -139,10 +137,13 @@ static void usb_reset(void) | |||
139 | DCTL = 0x802; /* Soft Disconnect */ | 137 | DCTL = 0x802; /* Soft Disconnect */ |
140 | 138 | ||
141 | OPHYPWR = 0; /* PHY: Power up */ | 139 | OPHYPWR = 0; /* PHY: Power up */ |
140 | OPHYUNK1 = 1; | ||
141 | OPHYUNK2 = 0xE3F; | ||
142 | OPHYCLK = SYNOPSYSOTG_CLOCK; | ||
142 | ORSTCON = 1; /* PHY: Assert Software Reset */ | 143 | ORSTCON = 1; /* PHY: Assert Software Reset */ |
143 | for (i = 0; i < 50; i++); | 144 | for (i = 0; i < 50; i++); |
144 | ORSTCON = 0; /* PHY: Deassert Software Reset */ | 145 | ORSTCON = 0; /* PHY: Deassert Software Reset */ |
145 | OPHYCLK = 0; /* PHY: 48MHz clock */ | 146 | OPHYUNK3 = 0x600; |
146 | 147 | ||
147 | GRSTCTL = 1; /* OTG: Assert Software Reset */ | 148 | GRSTCTL = 1; /* OTG: Assert Software Reset */ |
148 | while (GRSTCTL & 1); /* Wait for OTG to ack reset */ | 149 | while (GRSTCTL & 1); /* Wait for OTG to ack reset */ |
@@ -150,7 +151,7 @@ static void usb_reset(void) | |||
150 | 151 | ||
151 | GRXFSIZ = 0x00000200; /* RX FIFO: 512 bytes */ | 152 | GRXFSIZ = 0x00000200; /* RX FIFO: 512 bytes */ |
152 | GNPTXFSIZ = 0x02000200; /* Non-periodic TX FIFO: 512 bytes */ | 153 | GNPTXFSIZ = 0x02000200; /* Non-periodic TX FIFO: 512 bytes */ |
153 | GAHBCFG = 0x27; /* OTG AHB config: Unmask ints, burst length 4, DMA on */ | 154 | GAHBCFG = SYNOPSYSOTG_AHBCFG; |
154 | GUSBCFG = 0x1408; /* OTG: 16bit PHY and some reserved bits */ | 155 | GUSBCFG = 0x1408; /* OTG: 16bit PHY and some reserved bits */ |
155 | 156 | ||
156 | DCFG = 4; /* Address 0 */ | 157 | DCFG = 4; /* Address 0 */ |
@@ -375,12 +376,16 @@ void usb_drv_stall(int endpoint, bool stall, bool in) | |||
375 | void usb_drv_init(void) | 376 | void usb_drv_init(void) |
376 | { | 377 | { |
377 | /* Enable USB clock */ | 378 | /* Enable USB clock */ |
379 | #if CONFIG_CPU==S5L8701 | ||
378 | PWRCON &= ~0x4000; | 380 | PWRCON &= ~0x4000; |
379 | PWRCONEXT &= ~0x800; | 381 | PWRCONEXT &= ~0x800; |
380 | PCGCCTL = 0; | ||
381 | |||
382 | /* unmask irq */ | ||
383 | INTMSK |= INTMSK_USB_OTG; | 382 | INTMSK |= INTMSK_USB_OTG; |
383 | #elif CONFIG_CPU==S5L8702 | ||
384 | PWRCON(0) &= ~0x4; | ||
385 | PWRCON(1) &= ~0x8; | ||
386 | VIC0INTENABLE |= 1 << 19; | ||
387 | #endif | ||
388 | PCGCCTL = 0; | ||
384 | 389 | ||
385 | /* reset the beast */ | 390 | /* reset the beast */ |
386 | usb_reset(); | 391 | usb_reset(); |
@@ -394,8 +399,13 @@ void usb_drv_exit(void) | |||
394 | PCGCCTL = 1; /* Shut down PHY clock */ | 399 | PCGCCTL = 1; /* Shut down PHY clock */ |
395 | OPHYPWR = 0xF; /* PHY: Power down */ | 400 | OPHYPWR = 0xF; /* PHY: Power down */ |
396 | 401 | ||
402 | #if CONFIG_CPU==S5L8701 | ||
397 | PWRCON |= 0x4000; | 403 | PWRCON |= 0x4000; |
398 | PWRCONEXT |= 0x800; | 404 | PWRCONEXT |= 0x800; |
405 | #elif CONFIG_CPU==S5L8702 | ||
406 | PWRCON(0) |= 0x4; | ||
407 | PWRCON(1) |= 0x8; | ||
408 | #endif | ||
399 | } | 409 | } |
400 | 410 | ||
401 | void usb_init_device(void) | 411 | void usb_init_device(void) |
@@ -406,10 +416,16 @@ void usb_init_device(void) | |||
406 | 416 | ||
407 | /* Power up the core clocks to allow writing | 417 | /* Power up the core clocks to allow writing |
408 | to some registers needed to power it down */ | 418 | to some registers needed to power it down */ |
419 | PCGCCTL = 0; | ||
420 | #if CONFIG_CPU==S5L8701 | ||
409 | PWRCON &= ~0x4000; | 421 | PWRCON &= ~0x4000; |
410 | PWRCONEXT &= ~0x800; | 422 | PWRCONEXT &= ~0x800; |
411 | PCGCCTL = 0; | ||
412 | INTMSK |= INTMSK_USB_OTG; | 423 | INTMSK |= INTMSK_USB_OTG; |
424 | #elif CONFIG_CPU==S5L8702 | ||
425 | PWRCON(0) &= ~0x4; | ||
426 | PWRCON(1) &= ~0x8; | ||
427 | VIC0INTENABLE |= 1 << 19; | ||
428 | #endif | ||
413 | 429 | ||
414 | usb_drv_exit(); | 430 | usb_drv_exit(); |
415 | } | 431 | } |
@@ -441,8 +457,13 @@ void usb_init_device(void) | |||
441 | PCGCCTL = 1; /* Shut down PHY clock */ | 457 | PCGCCTL = 1; /* Shut down PHY clock */ |
442 | OPHYPWR = 0xF; /* PHY: Power down */ | 458 | OPHYPWR = 0xF; /* PHY: Power down */ |
443 | 459 | ||
460 | #if CONFIG_CPU==S5L8701 | ||
444 | PWRCON |= 0x4000; | 461 | PWRCON |= 0x4000; |
445 | PWRCONEXT |= 0x800; | 462 | PWRCONEXT |= 0x800; |
463 | #elif CONFIG_CPU==S5L8702 | ||
464 | PWRCON(0) |= 0x4; | ||
465 | PWRCON(1) |= 0x8; | ||
466 | #endif | ||
446 | } | 467 | } |
447 | 468 | ||
448 | void usb_enable(bool on) | 469 | void usb_enable(bool on) |