diff options
Diffstat (limited to 'firmware/target/arm/tms320dm320/uart-dm320.c')
-rw-r--r-- | firmware/target/arm/tms320dm320/uart-dm320.c | 120 |
1 files changed, 42 insertions, 78 deletions
diff --git a/firmware/target/arm/tms320dm320/uart-dm320.c b/firmware/target/arm/tms320dm320/uart-dm320.c index 38600e3c90..5671e47a9f 100644 --- a/firmware/target/arm/tms320dm320/uart-dm320.c +++ b/firmware/target/arm/tms320dm320/uart-dm320.c | |||
@@ -19,34 +19,25 @@ | |||
19 | #include "config.h" | 19 | #include "config.h" |
20 | #include "cpu.h" | 20 | #include "cpu.h" |
21 | #include "system.h" | 21 | #include "system.h" |
22 | #include "string.h" | ||
23 | #include "panic.h" | ||
22 | 24 | ||
23 | /* UART 0/1 */ | ||
24 | |||
25 | #define CONFIG_UART_BRSR 87 | ||
26 | #define MAX_UART_BUFFER 31 | 25 | #define MAX_UART_BUFFER 31 |
27 | static unsigned char uart1buffer[MAX_UART_BUFFER], uart1_send_buffer_ring[512]; | 26 | #define SEND_RING_SIZE 256 |
28 | int uart1_send_count=0,uart1_send_point=0; | 27 | #define RECIEVE_RING_SIZE 20 |
29 | int uart1read = 0, uart1write = 0, uart1count = 0; | ||
30 | 28 | ||
31 | /* | 29 | char |
32 | static void do_checksums(char *data, int len, char *xor, char *add) | 30 | // uart1_send_buffer_ring[SEND_RING_SIZE], |
33 | { | 31 | uart1_recieve_buffer_ring[RECIEVE_RING_SIZE]; |
34 | int i; | 32 | |
35 | *xor = data[0]; | 33 | //static unsigned int uart1_send_count, uart1_send_read, uart1_send_write; |
36 | *add = data[0]; | 34 | static unsigned int uart1_recieve_count, uart1_recieve_read, uart1_recieve_write; |
37 | for(i=1;i<len;i++) | ||
38 | { | ||
39 | *xor ^= data[i]; | ||
40 | *add += data[i]; | ||
41 | } | ||
42 | } | ||
43 | */ | ||
44 | 35 | ||
45 | void uart_init(void) | 36 | void uart_init(void) |
46 | { | 37 | { |
47 | // 8-N-1 | 38 | // 8-N-1 |
48 | IO_UART1_MSR=0x8000; | 39 | IO_UART1_MSR=0x8000; |
49 | IO_UART1_BRSR=CONFIG_UART_BRSR; | 40 | IO_UART1_BRSR=0x0057; |
50 | IO_UART1_RFCR = 0x8010; /* Trigger later */ | 41 | IO_UART1_RFCR = 0x8010; /* Trigger later */ |
51 | /* gio 27 is input, uart1 rx | 42 | /* gio 27 is input, uart1 rx |
52 | gio 28 is output, uart1 tx */ | 43 | gio 28 is output, uart1 tx */ |
@@ -54,10 +45,10 @@ void uart_init(void) | |||
54 | IO_GIO_DIR1 &= ~(1<<12); /* gio 28 */ | 45 | IO_GIO_DIR1 &= ~(1<<12); /* gio 28 */ |
55 | 46 | ||
56 | /* init the recieve buffer */ | 47 | /* init the recieve buffer */ |
57 | uart1read = 0; | 48 | uart1_recieve_count=0; |
58 | uart1write = 0; | 49 | uart1_recieve_read=0; |
59 | uart1count = 0; | 50 | uart1_recieve_write=0; |
60 | 51 | ||
61 | /* Enable the interrupt */ | 52 | /* Enable the interrupt */ |
62 | IO_INTC_EINT0 |= (1<<IRQ_UART1); | 53 | IO_INTC_EINT0 |= (1<<IRQ_UART1); |
63 | } | 54 | } |
@@ -71,18 +62,6 @@ void uart1_putc(char ch) | |||
71 | IO_UART1_DTRR=ch; | 62 | IO_UART1_DTRR=ch; |
72 | } | 63 | } |
73 | 64 | ||
74 | /* Unsigned integer to ASCII hexadecimal conversion */ | ||
75 | void uart1_putHex(unsigned int n) | ||
76 | { | ||
77 | unsigned int i; | ||
78 | |||
79 | for (i = 8; i != 0; i--) { | ||
80 | unsigned int digit = n >> 28; | ||
81 | uart1_putc(digit >= 10 ? digit - 10 + 'A' : digit + '0'); | ||
82 | n <<= 4; | ||
83 | } | ||
84 | } | ||
85 | |||
86 | void uart1_puts(const char *str) | 65 | void uart1_puts(const char *str) |
87 | { | 66 | { |
88 | char ch; | 67 | char ch; |
@@ -91,62 +70,47 @@ void uart1_puts(const char *str) | |||
91 | } | 70 | } |
92 | } | 71 | } |
93 | 72 | ||
94 | void uart1_gets(char *str, unsigned int size) | 73 | /* This function returns the number of bytes left in the queue after a read is done (negative if fail)*/ |
74 | int uart1_gets_queue(char *str, unsigned int size) | ||
95 | { | 75 | { |
96 | for (;;) { | 76 | if(uart1_recieve_count<size) |
97 | char ch; | 77 | return -uart1_recieve_count; |
98 | |||
99 | /* Wait for FIFO to contain something */ | ||
100 | while ((IO_UART1_RFCR & 0x3f) == 0); | ||
101 | |||
102 | /* Read character */ | ||
103 | ch = (char)IO_UART1_DTRR; | ||
104 | |||
105 | /* If CR, also echo LF, null-terminate, and return */ | ||
106 | if (ch == '\r') { | ||
107 | IO_UART1_DTRR='\n'; | ||
108 | if (size) { | ||
109 | *str++ = '\0'; | ||
110 | } | ||
111 | return; | ||
112 | } | ||
113 | |||
114 | /* Append to buffer */ | ||
115 | if (size) { | ||
116 | *str++ = ch; | ||
117 | --size; | ||
118 | } | ||
119 | } | ||
120 | } | ||
121 | 78 | ||
122 | bool uart1_getch(char *c) | 79 | if(uart1_recieve_read+size<RECIEVE_RING_SIZE) |
123 | { | ||
124 | if (uart1count > 0) | ||
125 | { | 80 | { |
126 | if(uart1read>MAX_UART_BUFFER) | 81 | memcpy(str,uart1_recieve_buffer_ring+uart1_recieve_read,size); |
127 | uart1read=0; | 82 | } |
128 | 83 | else | |
129 | *c = uart1buffer[uart1read++]; | 84 | { |
130 | uart1count--; | 85 | int tempcount=(RECIEVE_RING_SIZE-uart1_recieve_read); |
131 | return true; | 86 | memcpy(str,uart1_recieve_buffer_ring+uart1_recieve_read,tempcount); |
87 | memcpy(str+tempcount,uart1_recieve_buffer_ring,size-tempcount); | ||
132 | } | 88 | } |
133 | return false; | 89 | |
90 | uart1_recieve_count-=size; | ||
91 | |||
92 | if(uart1_recieve_read+size<RECIEVE_RING_SIZE) | ||
93 | uart1_recieve_read+=size; | ||
94 | else | ||
95 | uart1_recieve_read=size-(RECIEVE_RING_SIZE-uart1_recieve_read); | ||
96 | |||
97 | return uart1_recieve_count; | ||
134 | } | 98 | } |
135 | 99 | ||
136 | /* UART1 receive intterupt handler */ | 100 | /* UART1 receive interupt handler */ |
137 | void UART1(void) | 101 | void UART1(void) |
138 | { | 102 | { |
139 | while (IO_UART1_RFCR & 0x3f) | 103 | while (IO_UART1_RFCR & 0x3f) |
140 | { | 104 | { |
141 | if (uart1count > MAX_UART_BUFFER) | 105 | if (uart1_recieve_count > RECIEVE_RING_SIZE) |
142 | panicf("UART1 buffer overflow"); | 106 | panicf("UART1 buffer overflow"); |
143 | else | 107 | else |
144 | { | 108 | { |
145 | if(uart1write>MAX_UART_BUFFER) | 109 | if(uart1_recieve_write==RECIEVE_RING_SIZE) |
146 | uart1write=0; | 110 | uart1_recieve_write=0; |
147 | 111 | ||
148 | uart1buffer[uart1write++] = IO_UART1_DTRR & 0xff; | 112 | uart1_recieve_buffer_ring[uart1_recieve_write++] = IO_UART1_DTRR & 0xff; |
149 | uart1count++; | 113 | uart1_recieve_count++; |
150 | } | 114 | } |
151 | } | 115 | } |
152 | 116 | ||