diff options
Diffstat (limited to 'firmware/target/arm/tms320dm320/uart-dm320.c')
-rw-r--r-- | firmware/target/arm/tms320dm320/uart-dm320.c | 121 |
1 files changed, 83 insertions, 38 deletions
diff --git a/firmware/target/arm/tms320dm320/uart-dm320.c b/firmware/target/arm/tms320dm320/uart-dm320.c index 5e2ad5e2be..d68beb6e01 100644 --- a/firmware/target/arm/tms320dm320/uart-dm320.c +++ b/firmware/target/arm/tms320dm320/uart-dm320.c | |||
@@ -27,37 +27,48 @@ | |||
27 | 27 | ||
28 | #define MAX_UART_BUFFER 31 | 28 | #define MAX_UART_BUFFER 31 |
29 | #define SEND_RING_SIZE 256 | 29 | #define SEND_RING_SIZE 256 |
30 | #define RECIEVE_RING_SIZE 20 | 30 | #define RECEIVE_RING_SIZE 20 |
31 | 31 | ||
32 | char | 32 | char |
33 | // uart1_send_buffer_ring[SEND_RING_SIZE], | 33 | uart1_send_buffer_ring[SEND_RING_SIZE], |
34 | uart1_recieve_buffer_ring[RECIEVE_RING_SIZE]; | 34 | uart1_receive_buffer_ring[RECEIVE_RING_SIZE]; |
35 | 35 | ||
36 | //static unsigned int uart1_send_count, uart1_send_read, uart1_send_write; | 36 | static volatile int uart1_send_count, uart1_send_read, uart1_send_write; |
37 | static unsigned int uart1_recieve_count, uart1_recieve_read, uart1_recieve_write; | 37 | static volatile int uart1_receive_count, uart1_receive_read, uart1_receive_write; |
38 | 38 | ||
39 | void uart_init(void) | 39 | void uart_init(void) |
40 | { | 40 | { |
41 | // 8-N-1 | 41 | // 8-N-1 |
42 | IO_UART1_MSR = 0x8000; | 42 | IO_UART1_MSR = 0xC400; |
43 | IO_UART1_BRSR = 0x0057; | 43 | IO_UART1_BRSR = 0x0057; |
44 | IO_UART1_RFCR = 0x8010; /* Trigger later */ | 44 | IO_UART1_RFCR = 0x8020; /* Trigger later */ |
45 | IO_UART1_TFCR = 0x0000; /* Trigger level */ | ||
45 | /* gio 27 is input, uart1 rx | 46 | /* gio 27 is input, uart1 rx |
46 | gio 28 is output, uart1 tx */ | 47 | gio 28 is output, uart1 tx */ |
47 | IO_GIO_DIR1 |= (1<<11); /* gio 27 */ | 48 | IO_GIO_DIR1 |= (1<<11); /* gio 27 */ |
48 | IO_GIO_DIR1 &= ~(1<<12); /* gio 28 */ | 49 | IO_GIO_DIR1 &= ~(1<<12); /* gio 28 */ |
49 | 50 | ||
50 | /* init the recieve buffer */ | 51 | /* init the receive buffer */ |
51 | uart1_recieve_count=0; | 52 | uart1_receive_count=0; |
52 | uart1_recieve_read=0; | 53 | uart1_receive_read=0; |
53 | uart1_recieve_write=0; | 54 | uart1_receive_write=0; |
55 | |||
56 | /* init the send buffer */ | ||
57 | uart1_send_count=0; | ||
58 | uart1_send_read=0; | ||
59 | uart1_send_write=0; | ||
54 | 60 | ||
55 | /* Enable the interrupt */ | 61 | /* Enable the interrupt */ |
56 | IO_INTC_EINT0 |= INTR_EINT0_UART1; | 62 | IO_INTC_EINT0 |= INTR_EINT0_UART1; |
57 | } | 63 | } |
58 | 64 | ||
65 | |||
66 | /* This function is not interrupt driven */ | ||
59 | void uart1_putc(char ch) | 67 | void uart1_putc(char ch) |
60 | { | 68 | { |
69 | /* Wait for the interupt driven puts to finish */ | ||
70 | while(uart1_send_count>0); | ||
71 | |||
61 | /* Wait for room in FIFO */ | 72 | /* Wait for room in FIFO */ |
62 | while ((IO_UART1_TFCR & 0x3f) >= 0x20); | 73 | while ((IO_UART1_TFCR & 0x3f) >= 0x20); |
63 | 74 | ||
@@ -67,45 +78,73 @@ void uart1_putc(char ch) | |||
67 | 78 | ||
68 | void uart1_puts(const char *str, int size) | 79 | void uart1_puts(const char *str, int size) |
69 | { | 80 | { |
70 | int count=0; | 81 | if(size>SEND_RING_SIZE) |
71 | while (count<size) | 82 | panicf("Too much data passed to uart1_puts"); |
83 | |||
84 | /* Wait for the previous transfer to finish */ | ||
85 | while(uart1_send_count>0); | ||
86 | |||
87 | memcpy(uart1_send_buffer_ring, str, size); | ||
88 | |||
89 | /* Disable interrupt while modifying the pointers */ | ||
90 | IO_INTC_EINT0 &= ~INTR_EINT0_UART1; | ||
91 | |||
92 | uart1_send_count=size; | ||
93 | uart1_send_read=0; | ||
94 | |||
95 | /* prime the hardware buffer */ | ||
96 | while(((IO_UART1_TFCR & 0x3f) < 0x20) && (uart1_send_count > 0)) | ||
72 | { | 97 | { |
73 | uart1_putc(str[count]); | 98 | IO_UART1_DTRR=uart1_send_buffer_ring[uart1_send_read++]; |
74 | count++; | 99 | uart1_send_count--; |
75 | } | 100 | } |
101 | |||
102 | /* Enable interrupt */ | ||
103 | IO_INTC_EINT0 |= INTR_EINT0_UART1; | ||
104 | } | ||
105 | |||
106 | void uart1_clear_queue(void) | ||
107 | { | ||
108 | /* Disable interrupt while modifying the pointers */ | ||
109 | IO_INTC_EINT0 &= ~INTR_EINT0_UART1; | ||
110 | uart1_receive_write=0; | ||
111 | uart1_receive_count=0; | ||
112 | uart1_receive_read=0; | ||
113 | /* Enable interrupt */ | ||
114 | IO_INTC_EINT0 |= INTR_EINT0_UART1; | ||
76 | } | 115 | } |
77 | 116 | ||
78 | /* This function returns the number of bytes left in the queue after a read is done (negative if fail)*/ | 117 | /* This function returns the number of bytes left in the queue after a read is done (negative if fail)*/ |
79 | int uart1_gets_queue(char *str, unsigned int size) | 118 | int uart1_gets_queue(char *str, int size) |
80 | { | 119 | { |
120 | /* Disable the interrupt while modifying the pointers */ | ||
81 | IO_INTC_EINT0 &= ~INTR_EINT0_UART1; | 121 | IO_INTC_EINT0 &= ~INTR_EINT0_UART1; |
82 | int retval; | 122 | int retval; |
83 | 123 | ||
84 | if(uart1_recieve_count<size) | 124 | if(uart1_receive_count<size) |
85 | { | 125 | { |
86 | retval= -1; | 126 | retval= -1; |
87 | } | 127 | } |
88 | else | 128 | else |
89 | { | 129 | { |
90 | if(uart1_recieve_read+size<RECIEVE_RING_SIZE) | 130 | if(uart1_receive_read+size<=RECEIVE_RING_SIZE) |
91 | { | 131 | { |
92 | memcpy(str,uart1_recieve_buffer_ring+uart1_recieve_read,size); | 132 | memcpy(str,uart1_receive_buffer_ring+uart1_receive_read,size); |
133 | |||
134 | uart1_receive_read+=size; | ||
93 | } | 135 | } |
94 | else | 136 | else |
95 | { | 137 | { |
96 | int tempcount=(RECIEVE_RING_SIZE-uart1_recieve_read); | 138 | int tempcount=(RECEIVE_RING_SIZE-uart1_receive_read); |
97 | memcpy(str,uart1_recieve_buffer_ring+uart1_recieve_read,tempcount); | 139 | memcpy(str,uart1_receive_buffer_ring+uart1_receive_read,tempcount); |
98 | memcpy(str+tempcount,uart1_recieve_buffer_ring,size-tempcount); | 140 | memcpy(str+tempcount,uart1_receive_buffer_ring,size-tempcount); |
141 | |||
142 | uart1_receive_read=size-tempcount; | ||
99 | } | 143 | } |
100 | 144 | ||
101 | uart1_recieve_count-=size; | 145 | uart1_receive_count-=size; |
102 | 146 | ||
103 | if(uart1_recieve_read+size<RECIEVE_RING_SIZE) | 147 | retval=uart1_receive_count; |
104 | uart1_recieve_read+=size; | ||
105 | else | ||
106 | uart1_recieve_read=size-(RECIEVE_RING_SIZE-uart1_recieve_read); | ||
107 | |||
108 | retval=uart1_recieve_count; | ||
109 | } | 148 | } |
110 | 149 | ||
111 | /* Enable the interrupt */ | 150 | /* Enable the interrupt */ |
@@ -114,23 +153,29 @@ int uart1_gets_queue(char *str, unsigned int size) | |||
114 | return retval; | 153 | return retval; |
115 | } | 154 | } |
116 | 155 | ||
117 | /* UART1 receive interupt handler */ | 156 | /* UART1 receive/transmit interupt handler */ |
118 | void UART1(void) | 157 | void UART1(void) |
119 | { | 158 | { |
120 | while (IO_UART1_RFCR & 0x3f) | 159 | while (IO_UART1_RFCR & 0x3f) |
121 | { | 160 | { |
122 | if (uart1_recieve_count > RECIEVE_RING_SIZE) | 161 | if (uart1_receive_count > RECEIVE_RING_SIZE) |
123 | panicf("UART1 buffer overflow"); | 162 | panicf("UART1 receive buffer overflow"); |
124 | else | 163 | else |
125 | { | 164 | { |
126 | if(uart1_recieve_write>=RECIEVE_RING_SIZE) | 165 | if(uart1_receive_write>=RECEIVE_RING_SIZE) |
127 | uart1_recieve_write=0; | 166 | uart1_receive_write=0; |
128 | 167 | ||
129 | uart1_recieve_buffer_ring[uart1_recieve_write] = IO_UART1_DTRR & 0xff; | 168 | uart1_receive_buffer_ring[uart1_receive_write]=IO_UART1_DTRR & 0xff; |
130 | uart1_recieve_write++; | 169 | uart1_receive_write++; |
131 | uart1_recieve_count++; | 170 | uart1_receive_count++; |
132 | } | 171 | } |
133 | } | 172 | } |
134 | 173 | ||
174 | while ( ((IO_UART1_TFCR & 0x3f) < 0x20) && (uart1_send_count > 0) ) | ||
175 | { | ||
176 | IO_UART1_DTRR=uart1_send_buffer_ring[uart1_send_read++]; | ||
177 | uart1_send_count--; | ||
178 | } | ||
179 | |||
135 | IO_INTC_IRQ0 = INTR_IRQ0_UART1; | 180 | IO_INTC_IRQ0 = INTR_IRQ0_UART1; |
136 | } | 181 | } |