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Diffstat (limited to 'firmware/target/arm/tms320dm320/spi-dm320.c')
-rw-r--r--firmware/target/arm/tms320dm320/spi-dm320.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/firmware/target/arm/tms320dm320/spi-dm320.c b/firmware/target/arm/tms320dm320/spi-dm320.c
index f80c3884fc..f3b41add54 100644
--- a/firmware/target/arm/tms320dm320/spi-dm320.c
+++ b/firmware/target/arm/tms320dm320/spi-dm320.c
@@ -30,6 +30,7 @@
30 30
31#define GIO_TS_ENABLE (1<<2) 31#define GIO_TS_ENABLE (1<<2)
32#define GIO_RTC_ENABLE (1<<12) 32#define GIO_RTC_ENABLE (1<<12)
33#define GIO_BL_ENABLE (1<<13)
33 34
34struct spinlock spi_lock; 35struct spinlock spi_lock;
35 36
@@ -41,8 +42,9 @@ struct SPI_info {
41#define reg(a) ((volatile unsigned short *)(PHY_IO_BASE+a)) 42#define reg(a) ((volatile unsigned short *)(PHY_IO_BASE+a))
42struct SPI_info spi_targets[] = 43struct SPI_info spi_targets[] =
43{ 44{
44 [SPI_target_TSC2100] = { reg(0x0594), reg(0x058E), GIO_TS_ENABLE }, 45 [SPI_target_TSC2100] = { &IO_GIO_BITCLR1, &IO_GIO_BITSET1, GIO_TS_ENABLE },
45 [SPI_target_RX5X348AB] = { reg(0x058C), reg(0x0592), GIO_RTC_ENABLE }, 46 [SPI_target_RX5X348AB] = { &IO_GIO_BITSET0, &IO_GIO_BITCLR0, GIO_RTC_ENABLE },
47 [SPI_target_BACKLIGHT] = { &IO_GIO_BITCLR1, &IO_GIO_BITSET1, GIO_BL_ENABLE },
46}; 48};
47 49
48static void spi_disable_all_targets(void) 50static void spi_disable_all_targets(void)
@@ -92,8 +94,8 @@ int spi_block_transfer(enum SPI_target target,
92void spi_init(void) 94void spi_init(void)
93{ 95{
94 spinlock_init(&spi_lock); 96 spinlock_init(&spi_lock);
95 /* Set SCLK idle level = 1 */ 97 /* Set SCLK idle level = 0 */
96 IO_SERIAL0_MODE &= ~(1<<10); 98 IO_SERIAL0_MODE |= 1<<10;
97 /* Enable TX */ 99 /* Enable TX */
98 IO_SERIAL0_TX_ENABLE = 0x0001; 100 IO_SERIAL0_TX_ENABLE = 0x0001;
99 101