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Diffstat (limited to 'firmware/target/arm/tms320dm320/sansa-connect/tnetv105_usb_drv.h')
-rw-r--r--firmware/target/arm/tms320dm320/sansa-connect/tnetv105_usb_drv.h335
1 files changed, 335 insertions, 0 deletions
diff --git a/firmware/target/arm/tms320dm320/sansa-connect/tnetv105_usb_drv.h b/firmware/target/arm/tms320dm320/sansa-connect/tnetv105_usb_drv.h
new file mode 100644
index 0000000000..c31c9c6505
--- /dev/null
+++ b/firmware/target/arm/tms320dm320/sansa-connect/tnetv105_usb_drv.h
@@ -0,0 +1,335 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2021 by Tomasz Moń
11 * Ported from Sansa Connect TNETV105 UDC Linux driver
12 * Copyright (c) 2005 Zermatt Systems, Inc.
13 * Written by: Ben Bostwick
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 *
20 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
21 * KIND, either express or implied.
22 *
23 ****************************************************************************/
24
25#ifndef TNETV105_USB_DRV_H
26#define TNETV105_USB_DRV_H
27
28#include <stdint.h>
29
30#define DM320_AHB_PADDR 0x00060000
31#define DM320_VLYNQ_PADDR 0x70000000
32
33/* TNETV105 Memory Map */
34#define VLYNQ_BASE (0x70000000)
35
36#define TNETV_BASE (VLYNQ_BASE)
37#define TNETV_V2USB_BASE (TNETV_BASE + 0x00000200)
38#define TNETV_WDOG_BASE (TNETV_BASE + 0x00000280)
39#define TNETV_USB_HOST_BASE (TNETV_BASE + 0x00010000)
40#define TNETV_USB_DEVICE_BASE (TNETV_BASE + 0x00020000)
41
42#define TNETV_V2USB_REG(x) (TNETV_V2USB_BASE + (x))
43
44#define TNETV_V2USB_RESET (TNETV_V2USB_REG(0x00))
45#define TNETV_V2USB_CLK_PERF (TNETV_V2USB_REG(0x04))
46#define TNETV_V2USB_CLK_MODE (TNETV_V2USB_REG(0x08))
47#define TNETV_V2USB_CLK_CFG (TNETV_V2USB_REG(0x0C))
48#define TNETV_V2USB_CLK_WKUP (TNETV_V2USB_REG(0x10))
49#define TNETV_V2USB_CLK_PWR (TNETV_V2USB_REG(0x14))
50
51#define TNETV_V2USB_PID_VID (TNETV_V2USB_REG(0x28))
52
53#define TNETV_V2USB_GPIO_DOUT (TNETV_V2USB_REG(0x40))
54#define TNETV_V2USB_GPIO_DIN (TNETV_V2USB_REG(0x44))
55#define TNETV_V2USB_GPIO_DIR (TNETV_V2USB_REG(0x48))
56#define TNETV_V2USB_GPIO_FS (TNETV_V2USB_REG(0x4C))
57#define TNETV_V2USB_GPIO_INTF (TNETV_V2USB_REG(0x50))
58#define TNETV_V2USB_GPIO_EOI (TNETV_V2USB_REG(0x54))
59
60#define TNETV_USB_DEVICE_REG(x) (TNETV_USB_DEVICE_BASE + (x))
61
62#define TNETV_USB_REV (TNETV_USB_DEVICE_REG(0x00))
63#define TNETV_USB_TX_CTL (TNETV_USB_DEVICE_REG(0x04))
64#define TNETV_USB_TX_TEARDOWN (TNETV_USB_DEVICE_REG(0x08))
65#define TNETV_USB_RX_CTL (TNETV_USB_DEVICE_REG(0x14))
66#define TNETV_USB_RX_TEARDOWN (TNETV_USB_DEVICE_REG(0x18))
67#define TNETV_USB_TX_ENDIAN_CTL (TNETV_USB_DEVICE_REG(0x40))
68#define TNETV_USB_RX_ENDIAN_CTL (TNETV_USB_DEVICE_REG(0x44))
69
70#define TNETV_USB_RX_FREE_BUF_CNT(ch) (TNETV_USB_DEVICE_REG(0x140 + ((ch) * 4)))
71
72#define TNETV_USB_TX_INT_STATUS (TNETV_USB_DEVICE_REG(0x170))
73#define TNETV_USB_TX_INT_EN (TNETV_USB_DEVICE_REG(0x178))
74#define TNETV_USB_TX_INT_DIS (TNETV_USB_DEVICE_REG(0x17C))
75#define TNETV_USB_VBUS_INT (TNETV_USB_DEVICE_REG(0x180))
76#define TNETV_USB_VBUS_EOI (TNETV_USB_DEVICE_REG(0x184))
77#define TNETV_USB_RX_INT_STATUS (TNETV_USB_DEVICE_REG(0x190))
78#define TNETV_USB_RX_INT_EN (TNETV_USB_DEVICE_REG(0x198))
79#define TNETV_USB_RX_INT_DIS (TNETV_USB_DEVICE_REG(0x19C))
80
81#define TNETV_USB_RESET_CMPL (TNETV_USB_DEVICE_REG(0x1A0))
82#define TNETV_CPPI_STATE (TNETV_USB_DEVICE_REG(0x1A4))
83
84#define TNETV_USB_STATUS (TNETV_USB_DEVICE_REG(0x200))
85#define TNETV_USB_CTRL (TNETV_USB_DEVICE_REG(0x204))
86#define TNETV_USB_IF_STATUS (TNETV_USB_DEVICE_REG(0x210))
87#define TNETV_USB_IF_ERR (TNETV_USB_DEVICE_REG(0x214))
88#define TNETV_USB_IF_SM (TNETV_USB_DEVICE_REG(0x218))
89
90#define TNETV_USB_EP0_CFG (TNETV_USB_DEVICE_REG(0x220))
91#define TNETV_USB_EP0_CNT (TNETV_USB_DEVICE_REG(0x224))
92
93#define TNETV_USB_EPx_CFG(x) (TNETV_USB_DEVICE_REG(0x220 + (0x10 * (x))))
94#define TNETV_USB_EPx_IN_CNT(x) (TNETV_USB_DEVICE_REG(0x224 + (0x10 * (x))))
95#define TNETV_USB_EPx_OUT_CNT(x) (TNETV_USB_DEVICE_REG(0x228 + (0x10 * (x))))
96#define TNETV_USB_EPx_ADR(x) (TNETV_USB_DEVICE_REG(0x22C + (0x10 * (x))))
97
98/* USB CPPI Config registers (0x300 - 0x30C) */
99#define TNETV_USB_RNDIS_MODE (TNETV_USB_DEVICE_REG(0x300))
100#define TNETV_USB_CELL_DMA_EN (TNETV_USB_DEVICE_REG(0x30C))
101
102#define TNETV_USB_RAW_INT (TNETV_USB_DEVICE_REG(0x310))
103#define TNETV_USB_RAW_EOI (TNETV_USB_DEVICE_REG(0x314))
104
105/* USB DMA setup RAM (0x800 - 0x8FF) */
106#define TNETV_DMA_BASE (TNETV_USB_DEVICE_BASE + 0x800)
107#define TNETV_DMA_TX_STATE(ch, wd) ((uint32_t *) ((TNETV_DMA_BASE) + ((ch) * 0x40) + ((wd) * 4)))
108#define TNETV_DMA_TX_CMPL(ch) ((TNETV_DMA_BASE) + ((ch) * 0x40) + 0x1C)
109
110#define TNETV_CPPI_TX_WORD_HDP 0
111
112#define TNETV_DMA_RX_STATE(ch, wd) ((uint32_t *) ((TNETV_DMA_BASE) + ((ch) * 0x40) + 0x20 + ((wd) * 4)))
113#define TNETV_DMA_RX_CMPL(ch) ((TNETV_DMA_BASE) + ((ch) * 0x40) + 0x3C)
114
115#define TNETV_CPPI_RX_WORD_HDP 1
116
117#define TNETV_DMA_NUM_CHANNELS 3
118
119#define TNETV_DMA_TX_NUM_WORDS 6
120#define TNETV_DMA_RX_NUM_WORDS 7
121
122
123/* USB Buffer RAM (0x1000 - 0x1A00) */
124#define TNETV_EP_DATA_ADDR(x) ((uint32_t *) ((TNETV_USB_DEVICE_BASE) + 0x1000 + (x)))
125
126#define TNETV_EP_DATA_SIZE (0xA00)
127
128#define TNETV_V2USB_RESET_DEV (1 << 0)
129
130#define TNETV_USB_CELL_DMA_EN_RX (1 << 0)
131#define TNETV_USB_CELL_DMA_EN_TX (1 << 1)
132
133#define TNETV_V2USB_CLK_WKUP_VBUS (1 << 12)
134
135#define DM320_VLYNQ_INTPND_PHY ((DM320_AHB_PADDR) + 0x0314)
136
137
138/* macro to convert from a linux pointer to a physical address
139 * to be sent over the VLYNQ bus. The dm320 vlynq rx registers are
140 * set up so the base address is the physical address of RAM
141 */
142#define __dma_to_vlynq_phys(addr) ((((uint32_t) (addr)) - 0x01000000))
143#define __vlynq_phys_to_dma(addr) ((((uint32_t) (addr)) + 0x01000000))
144
145//----------------------------------------------------------------------
146
147#define USB_FULL_SPEED_MAXPACKET 64
148#define USB_HIGH_SPEED_MAXPACKET 512
149
150/* WORD offsets into the data memory */
151#define EP0_MAX_PACKET_SIZE 64 /* Control ep - 64 bytes */
152#define EP1_MAX_PACKET_SIZE 512 /* Bulk ep - 512 bytes */
153#define EP2_MAX_PACKET_SIZE 512 /* Bulk ep - 512 bytes */
154#define EP3_MAX_PACKET_SIZE 64 /* Int ep - 64 bytes */
155#define EP4_MAX_PACKET_SIZE 64 /* Int ep - 64 bytes */
156
157/* BEN TODO: fix this crap */
158#define EP0_OUTPKT_ADDRESS 0
159#define EP0_INPKT_ADDRESS (EP0_MAX_PACKET_SIZE)
160#define EP1_XBUFFER_ADDRESS (EP0_MAX_PACKET_SIZE << 1)
161#define EP1_YBUFFER_ADDRESS (EP1_XBUFFER_ADDRESS + EP1_MAX_PACKET_SIZE)
162#define EP2_XBUFFER_ADDRESS (EP1_XBUFFER_ADDRESS + (EP1_MAX_PACKET_SIZE << 1))
163#define EP2_YBUFFER_ADDRESS (EP2_XBUFFER_ADDRESS + EP2_MAX_PACKET_SIZE)
164#define EP3_XBUFFER_ADDRESS (EP2_XBUFFER_ADDRESS + (EP2_MAX_PACKET_SIZE << 1))
165#define EP3_YBUFFER_ADDRESS (EP3_XBUFFER_ADDRESS + EP3_MAX_PACKET_SIZE)
166#define EP4_XBUFFER_ADDRESS (EP3_XBUFFER_ADDRESS + (EP3_MAX_PACKET_SIZE << 1))
167#define EP4_YBUFFER_ADDRESS (EP4_XBUFFER_ADDRESS + EP4_MAX_PACKET_SIZE)
168#define EP5_XBUFFER_ADDRESS (EP4_XBUFFER_ADDRESS + (EP4_MAX_PACKET_SIZE << 1))
169#define EP5_YBUFFER_ADDRESS (EP5_XBUFFER_ADDRESS + EP1_MAX_PACKET_SIZE)
170#define EP6_XBUFFER_ADDRESS (EP5_XBUFFER_ADDRESS + (EP1_MAX_PACKET_SIZE << 1))
171#define EP6_YBUFFER_ADDRESS (EP6_XBUFFER_ADDRESS + EP2_MAX_PACKET_SIZE)
172#define EP7_XBUFFER_ADDRESS (EP6_XBUFFER_ADDRESS + (EP2_MAX_PACKET_SIZE << 1))
173#define EP7_YBUFFER_ADDRESS (EP7_XBUFFER_ADDRESS + EP3_MAX_PACKET_SIZE)
174#define EP8_XBUFFER_ADDRESS (EP7_XBUFFER_ADDRESS + (EP3_MAX_PACKET_SIZE << 1))
175#define EP8_YBUFFER_ADDRESS (EP8_XBUFFER_ADDRESS + EP4_MAX_PACKET_SIZE)
176
177#define SETUP_PKT_DATA_SIZE 8
178
179#define EP0_BUF_SIZE_8 0
180#define EP0_BUF_SIZE_16 1
181#define EP0_BUF_SIZE_32 2
182#define EP0_BUF_SIZE_64 3
183
184/* USB Status register */
185typedef struct {
186 uint32_t rsvd1 : 5;
187 uint32_t ep0_out_ack : 1;
188 uint32_t rsvd2 : 1;
189 uint32_t ep0_in_ack : 1;
190 uint32_t rsvd3 : 16;
191 uint32_t setup_ow : 1;
192 uint32_t setup : 1;
193 uint32_t vbus : 1;
194 uint32_t resume : 1;
195 uint32_t suspend : 1;
196 uint32_t reset : 1;
197 uint32_t sof : 1;
198 uint32_t any_int : 1;
199} UsbStatusStruct;
200
201typedef union {
202 uint32_t val;
203 UsbStatusStruct f;
204} UsbStatusType;
205
206/* USB Function control register */
207typedef struct {
208 uint32_t dir : 1;
209 uint32_t hs_test_mode : 3;
210 uint32_t rsvd1 : 1;
211 uint32_t wkup_en : 1;
212 uint32_t low_pwr_en : 1;
213 uint32_t connect : 1;
214 uint32_t rsvd2 : 4;
215 uint32_t ep0_in_int_en : 1;
216 uint32_t ep0_out_int_en : 1;
217 uint32_t err_cnt_en : 2;
218 uint32_t func_addr : 7;
219 uint32_t speed : 1;
220 uint32_t setupow_int_en : 1;
221 uint32_t setup_int_en : 1;
222 uint32_t vbus_int_en : 1;
223 uint32_t resume_int_en : 1;
224 uint32_t suspend_int_en : 1;
225 uint32_t reset_int_en : 1;
226 uint32_t sof_int_en : 1;
227 uint32_t rsvd3 : 1;
228} UsbCtrlStruct;
229
230typedef union {
231 uint32_t val;
232 UsbCtrlStruct f;
233} UsbCtrlType;
234
235/* Endpoint 0 Control Register */
236typedef struct {
237 uint32_t buf_size : 2;
238 uint32_t in_int_en : 1;
239 uint32_t in_stall : 1;
240 uint32_t dbl_buf : 1;
241 uint32_t in_toggle : 1;
242 uint32_t in_nak_int_en : 1;
243 uint32_t in_en : 1;
244 uint32_t res3 : 10;
245 uint32_t out_int_en : 1;
246 uint32_t out_stall : 1;
247 uint32_t res4 : 1;
248 uint32_t out_toggle : 1;
249 uint32_t out_nak_int_en : 1;
250 uint32_t out_en : 1;
251 uint32_t res6 : 8;
252} UsbEp0CtrlStruct;
253
254typedef union {
255 uint32_t val;
256 UsbEp0CtrlStruct f;
257} UsbEp0CtrlType;
258
259/* Endpoint 0 current packet size register */
260typedef struct {
261 uint32_t in_xbuf_cnt : 7;
262 uint32_t in_xbuf_nak : 1;
263 uint32_t in_ybuf_cnt : 7;
264 uint32_t in_ybuf_nak : 1;
265 uint32_t out_xbuf_cnt : 7;
266 uint32_t out_xbuf_nak : 1;
267 uint32_t out_ybuf_cnt : 7;
268 uint32_t out_ybuf_nak : 1;
269} UsbEp0ByteCntStruct;
270
271typedef union {
272 uint32_t val;
273 UsbEp0ByteCntStruct f;
274} UsbEp0ByteCntType;
275
276/* Endpoint n Configuration and Control register */
277typedef struct {
278 uint32_t res1 : 1;
279 uint32_t in_toggle_rst : 1;
280 uint32_t in_ack_int : 1;
281 uint32_t in_stall : 1;
282 uint32_t in_dbl_buf : 1;
283 uint32_t in_toggle : 1;
284 uint32_t in_nak_int : 1;
285 uint32_t in_en : 1;
286 uint32_t res2 : 1;
287 uint32_t out_toggle_rst : 1;
288 uint32_t out_ack_int : 1;
289 uint32_t out_stall : 1;
290 uint32_t out_dbl_buf : 1;
291 uint32_t out_toggle : 1;
292 uint32_t out_nak_int : 1;
293 uint32_t out_en : 1;
294 uint32_t in_buf_size : 8;
295 uint32_t out_buf_size : 8;
296} UsbEpCfgCtrlStruct;
297
298typedef union {
299 uint32_t val;
300 UsbEpCfgCtrlStruct f;
301} UsbEpCfgCtrlType;
302
303/* Endpoint n XY Buffer Start Address register */
304typedef struct {
305 uint8_t xBuffStartAddrIn;
306 uint8_t yBuffStartAddrIn;
307 uint8_t xBuffStartAddrOut;
308 uint8_t yBuffStartAddrOut;
309} UsbEpStartAddrStruct;
310
311typedef union {
312 uint32_t val;
313 UsbEpStartAddrStruct f;
314} UsbEpStartAddrType;
315
316/* Endpoint n Packet Control register */
317typedef struct {
318 uint32_t xBufPacketCount : 11;
319 uint32_t res1 : 4;
320 uint32_t xbuf_nak : 1;
321 uint32_t yBufPacketCount : 11;
322 uint32_t res2 : 4;
323 uint32_t ybuf_nak : 1;
324} UsbEpByteCntStruct;
325
326typedef union {
327 uint32_t val;
328 UsbEpByteCntStruct f;
329} UsbEpByteCntType;
330
331#define tnetv_usb_reg_read(x) (*((volatile uint32_t *) (x)))
332#define tnetv_usb_reg_write(x, val) (*((volatile uint32_t *) (x)) = (uint32_t) (val))
333
334
335#endif
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