diff options
Diffstat (limited to 'firmware/target/arm/tms320dm320/sansa-connect/tnetv105_cppi.h')
-rw-r--r-- | firmware/target/arm/tms320dm320/sansa-connect/tnetv105_cppi.h | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/firmware/target/arm/tms320dm320/sansa-connect/tnetv105_cppi.h b/firmware/target/arm/tms320dm320/sansa-connect/tnetv105_cppi.h new file mode 100644 index 0000000000..9d0ac37cd0 --- /dev/null +++ b/firmware/target/arm/tms320dm320/sansa-connect/tnetv105_cppi.h | |||
@@ -0,0 +1,144 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id: $ | ||
9 | * | ||
10 | * Copyright (C) 2021 by Tomasz Moń | ||
11 | * Copied with minor modifications from Sansa Connect Linux driver | ||
12 | * Copyright (c) 2005 Zermatt Systems, Inc. | ||
13 | * Written by: Ben Bostwick | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | |||
25 | #ifndef TNETV105_CPPI_H | ||
26 | #define TNETV105_CPPI_H | ||
27 | |||
28 | #include <stdint.h> | ||
29 | |||
30 | typedef uint32_t dma_addr_t; | ||
31 | #define USB_CPPI_LOGGING 0 | ||
32 | #define EAGAIN 11 /* Try again */ | ||
33 | #define CPPI_RX_NUM_BUFS 129 | ||
34 | #define CPPI_INFO_MEM_SIZE (2 * CPPI_RX_NUM_BUFS * sizeof(cppi_rcb) + 4 * 2 * sizeof(cppi_tcb)) | ||
35 | |||
36 | #define CPPI_NUM_CHANNELS 4 | ||
37 | #define CPPI_MAX_FRAG 0xFE00 | ||
38 | |||
39 | struct cppi_info; | ||
40 | |||
41 | typedef struct | ||
42 | { | ||
43 | uint32_t HNext; /*< Hardware's pointer to next buffer descriptor */ | ||
44 | uint32_t BufPtr; /*< Pointer to the data buffer */ | ||
45 | uint32_t Off_BLen; /*< Contains buffer offset and buffer length */ | ||
46 | uint32_t mode; /*< SOP, EOP, Ownership, EOQ, Teardown, Q Starv, Length */ | ||
47 | void *Next; | ||
48 | void *Eop; | ||
49 | dma_addr_t dma_handle; | ||
50 | uint32_t dummy; | ||
51 | |||
52 | } cppi_tcb; | ||
53 | |||
54 | typedef struct | ||
55 | { | ||
56 | uint32_t HNext; /*< Hardware's pointer to next buffer descriptor */ | ||
57 | uint32_t BufPtr; /*< Pointer to the data buffer */ | ||
58 | uint32_t Off_BLen; /*< Contains buffer offset and buffer length */ | ||
59 | uint32_t mode; /*< SOP, EOP, Ownership, EOQ, Teardown Complete bits */ | ||
60 | void *Next; | ||
61 | void *Eop; | ||
62 | dma_addr_t dma_handle; | ||
63 | uint32_t fake_bytes; | ||
64 | |||
65 | } cppi_rcb; | ||
66 | |||
67 | typedef struct cppi_txcntl | ||
68 | { | ||
69 | cppi_tcb *TcbPool; | ||
70 | cppi_tcb *TxActQueueHead; | ||
71 | cppi_tcb *TxActQueueTail; | ||
72 | uint32_t TxActQueueCount; | ||
73 | uint32_t TxActive; | ||
74 | cppi_tcb *LastTcbProcessed; | ||
75 | char *TcbStart; | ||
76 | dma_addr_t tcb_start_dma_addr; | ||
77 | int TxNumBuffers; | ||
78 | |||
79 | #ifdef _CPHAL_STATS | ||
80 | uint32_t TxMisQCnt; | ||
81 | uint32_t TxEOQCnt; | ||
82 | uint32_t TxPacketsServiced; | ||
83 | uint32_t TxMaxServiced; | ||
84 | uint32_t NumTxInt; | ||
85 | #endif | ||
86 | } cppi_txcntl; | ||
87 | |||
88 | |||
89 | typedef struct cppi_rxcntl | ||
90 | { | ||
91 | cppi_rcb *RcbPool; | ||
92 | cppi_rcb *RxActQueueHead; | ||
93 | cppi_rcb *RxActQueueTail; | ||
94 | uint32_t RxActQueueCount; | ||
95 | uint32_t RxActive; | ||
96 | char *RcbStart; | ||
97 | dma_addr_t rcb_start_dma_addr; | ||
98 | int RxNumBuffers; | ||
99 | |||
100 | cppi_rcb *RxFakeRcvHead; | ||
101 | cppi_rcb *RxFakeRcvTail; | ||
102 | |||
103 | #ifdef _CPHAL_STATS | ||
104 | uint32_t RxMisQCnt; | ||
105 | uint32_t RxEOQCnt; | ||
106 | uint32_t RxMaxServiced; | ||
107 | uint32_t RxPacketsServiced; | ||
108 | uint32_t NumRxInt; | ||
109 | #endif | ||
110 | } cppi_rxcntl; | ||
111 | |||
112 | typedef struct cppi_info | ||
113 | { | ||
114 | struct cppi_txcntl tx_ctl[CPPI_NUM_CHANNELS]; | ||
115 | struct cppi_rxcntl rx_ctl[CPPI_NUM_CHANNELS]; | ||
116 | |||
117 | uint8_t dma_mem[CPPI_INFO_MEM_SIZE]; | ||
118 | int dma_size; | ||
119 | dma_addr_t dma_handle; | ||
120 | |||
121 | } cppi_info; | ||
122 | |||
123 | #define tnetv_cppi_rx_int_recv_check(cppi, ch) (((cppi)->rx_ctl[(ch)].RxFakeRcvHead) ? 1 : 0) | ||
124 | |||
125 | int tnetv_cppi_init_tcb(struct cppi_info *cppi, int ch); | ||
126 | int tnetv_cppi_flush_tx_queue(struct cppi_info *cppi, int ch); | ||
127 | int tnetv_cppi_send(struct cppi_info *cppi, int ch, dma_addr_t buf, unsigned length, int send_zlp); | ||
128 | int tnetv_cppi_tx_int(struct cppi_info *cppi, int ch); | ||
129 | void tnetv_cppi_free_tcb(struct cppi_info *cppi, int ch); | ||
130 | |||
131 | int tnetv_cppi_init_rcb(struct cppi_info *cppi, int ch); | ||
132 | int tnetv_cppi_flush_rx_queue(struct cppi_info *cppi, int ch); | ||
133 | int tnetv_cppi_rx_return(struct cppi_info *cppi, int ch, cppi_rcb *done_rcb); | ||
134 | int tnetv_cppi_rx_queue_add(struct cppi_info *cppi, int ch, dma_addr_t buf, unsigned length); | ||
135 | int tnetv_cppi_rx_int(struct cppi_info *cppi, int ch); | ||
136 | int tnetv_cppi_rx_int_recv(struct cppi_info *cppi, int ch, int *buf_size, void *buf, int maxpacket); | ||
137 | void tnetv_cppi_free_rcb(struct cppi_info *cppi, int ch); | ||
138 | |||
139 | void tnetv_cppi_init(struct cppi_info *cppi); | ||
140 | void tnetv_cppi_cleanup(struct cppi_info *cppi); | ||
141 | |||
142 | void tnetv_cppi_dump_info(struct cppi_info *cppi); | ||
143 | |||
144 | #endif | ||