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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2002 by Linus Nielsen Feltzing
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22/* Arm bootloader and startup code based on startup.s from the iPodLinux loader
23 *
24 * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
25 * Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org>
26 *
27 */
28
29#include "config.h"
30#include "cpu.h"
31
32 .section .init.text,"ax",%progbits
33
34 .extern irq
35 .extern fiq
36 .extern UIE
37 .extern main
38
39 .global start
40
41/* Telechips firmware files start with a 32-byte header, as part of the code. */
42
43start:
44#ifdef TCCBOOT
45 /* Add -DTCCBOOT to EXTRA_DEFINES in the bootloader Makefile to
46 enable building the bootloader to be appended to the end of the
47 original firmware, dual-booting based on a key-press.
48
49 The following two values are filled in by mktccboot.
50 */
51of_entrypoint: .word 0 /* Saved entrypoint of original firmware*/
52bl_entrypoint: .word 0 /* Location in RAM of the start of our bootloader */
53
54#else
55// ldr pc, =start_loc /* jump to the main entry point */
56 b start_loc
57
58 .word 0xffff0601 /* Unknown magic */
59 .word 0x3a726556 /* "Ver:" */
60 .word 0x31373030 /* "0071" */
61 .word 0 /* First CRC32 */
62 .word 0 /* Unknown - always 0 */
63 .word 0 /* Second CRC32 */
64 .word 0 /* length of firmware file */
65
66#if defined(LOGIK_DAX) || defined(SANSA_C100)
67 /* Some original firmwares have 0x40 bytes of zeroes here - we
68 don't know why, but err on the side of caution and include it
69 here. */
70 .space 0x40
71#endif
72#endif
73
74start_loc:
75
76#ifdef BOOTLOADER
77
78/*
79 If we are appended to the OF (i.e. dual-booting), do a simple GPIO
80 button check, and branch to the OF's entry point (saved by mktccboot)
81 if not active
82*/
83
84#ifdef TCCBOOT
85 mov r0, #0x80000000
86#if defined(LOGIK_DAX) || defined(SANSA_C100)
87 ldr r0, [r0, #0x300] /* Hold button is GPIO A, pin 0x2 */
88 tst r0, #0x2
89#elif defined(SANSA_M200)
90 ldr r0, [r0, #0x310] /* Hold button is GPIO B, pin 0x200 */
91 tst r0, #0x200
92#elif defined(IAUDIO_7)
93 ldr r0, [r0, #0x300] /* Hold button is !GPIO A, pin 0x2 */
94 tst r0, #0x2
95#else
96 #error No bootup key detection implemented for this target
97#endif
98
99 ldrne pc, of_entrypoint /* Jump to OF if HOLD button not pressed */
100#endif /* TCCBOOT */
101
102/* We are now definitely executing the bootloader, so we relocate to the
103 linked address (see boot.lds) - 1MB from the end of DRAM.
104*/
105
106#ifdef TCCBOOT
107 ldr r0, bl_entrypoint
108#else
109 mov r0, #0x20000000 /* Otherwise, load address is the start of DRAM */
110#endif
111 mov r1, #0x20000000 /* Destination: 1MB from end of DRAM */
112 add r1, r1, #((MEMORYSIZE - 1) * 0x100000)
113
114 ldr r2, =_dataend
1151:
116 cmp r2, r1
117 ldrhi r3, [r0], #4
118 strhi r3, [r1], #4
119 bhi 1b
120
121 ldr pc, =copied_start /* jump to the relocated start_loc: */
122copied_start:
123#endif /* BOOTLOADER */
124
125 /* Set up stack for IRQ mode */
126 mov r0,#0xd2
127 msr cpsr, r0
128 ldr sp, =irq_stack
129
130 /* Set up stack for FIQ mode */
131 mov r0,#0xd1
132 msr cpsr, r0
133 ldr sp, =fiq_stack
134
135#ifndef BOOTLOADER
136 /* Load the banked FIQ mode registers with useful values here.
137 These values will be used in the FIQ handler in pcm-telechips.c */
138 .equ DADO_BASE, 0x80000020
139
140 ldr r10, =DADO_BASE
141 ldr r11, =dma_play_data
142#endif
143
144 /* Let svc, abort and undefined modes use irq stack */
145 msr cpsr, #0xd3
146 ldr sp, =irq_stack
147 msr cpsr, #0xd7
148 ldr sp, =irq_stack
149 msr cpsr, #0xdb
150 ldr sp, =irq_stack
151
152 /* Switch to sys mode */
153 mov r0,#0xdf
154 msr cpsr, r0
155 ldr sp, =stackend
156
157 /* Copy exception handler code to address 0 */
158 mov r2, #0x0
159 ldr r3, =vectors_start
160 ldr r4, =vectors_end
1611:
162 cmp r4, r3
163 ldrhi r5, [r3], #4
164 strhi r5, [r2], #4
165 bhi 1b
166
167 /* Initialise bss section to zero */
168 ldr r2, =_edata
169 ldr r3, =_end
170 mov r4, #0
1711:
172 cmp r3, r2
173 strhi r4, [r2], #4
174 bhi 1b
175
176 /* Set up some stack and munge it with 0xdeadbeef */
177 ldr sp, =stackend
178 mov r3, sp
179 ldr r2, =stackbegin
180 ldr r4, =0xdeadbeef
1811:
182 cmp r3, r2
183 strhi r4, [r2], #4
184 bhi 1b
185
186 bl main
187 /* main() should never return */
188
189/* Exception handlers. Will be copied to address 0 after memory remapping */
190vectors_start:
191 ldr pc, [pc, #24]
192 ldr pc, [pc, #24]
193 ldr pc, [pc, #24]
194 ldr pc, [pc, #24]
195 ldr pc, [pc, #24]
196 ldr pc, [pc, #24]
197 ldr pc, [pc, #24]
198 ldr pc, [pc, #24]
199
200 /* Exception vectors */
201 .global vectors
202vectors:
203 .word start
204 .word undef_instr_handler
205 .word software_int_handler
206 .word prefetch_abort_handler
207 .word data_abort_handler
208 .word reserved_handler
209 .word irq_handler
210 .word fiq_handler
211vectors_end:
212
213 .text
214
215irq_handler:
216 stmfd sp!, {r0-r3, r12, lr}
217 bl irq
218 ldmfd sp!, {r0-r3, r12, lr}
219 subs pc, lr, #4
220
221/* Align stacks to cache line boundary */
222 .balign 16
223
224/* 256 words of IRQ stack */
225 .space 256*4
226irq_stack:
227
228/* 256 words of FIQ stack */
229 .space 256*4
230fiq_stack:
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-04 23:51:26 +0000