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Diffstat (limited to 'firmware/target/arm/system-target.h')
-rw-r--r--firmware/target/arm/system-target.h13
1 files changed, 6 insertions, 7 deletions
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h
index 6dc317e427..ed8d90c627 100644
--- a/firmware/target/arm/system-target.h
+++ b/firmware/target/arm/system-target.h
@@ -52,7 +52,6 @@ static inline void udelay(unsigned usecs)
52 while (TIME_BEFORE(USEC_TIMER, stop)); 52 while (TIME_BEFORE(USEC_TIMER, stop));
53} 53}
54 54
55#ifdef CPU_PP502x
56static inline unsigned int current_core(void) 55static inline unsigned int current_core(void)
57{ 56{
58 /* 57 /*
@@ -63,14 +62,16 @@ static inline unsigned int current_core(void)
63 */ 62 */
64 unsigned int core; 63 unsigned int core;
65 asm volatile ( 64 asm volatile (
66 "mov %0, #0x60000000 \r\n" /* PROCESSOR_ID */ 65 "ldrb %0, [%1] \n" /* Just load the LSB */
67 "ldrb %0, [%0] \r\n" /* Just load the LSB */ 66 "mov %0, %0, lsr #7 \n" /* Bit 7 => index */
68 "mov %0, %0, lsr #7 \r\n" /* Bit 7 => index */ 67 : "=r"(core) /* CPU=0, COP=1 */
69 : "=&r"(core) /* CPU=0, COP=1 */ 68 : "r"(&PROCESSOR_ID)
70 ); 69 );
71 return core; 70 return core;
72} 71}
73 72
73#ifdef CPU_PP502x
74
74#ifndef BOOTLOADER 75#ifndef BOOTLOADER
75#define CACHE_FUNCTIONS_AS_CALL 76#define CACHE_FUNCTIONS_AS_CALL
76 77
@@ -81,8 +82,6 @@ void invalidate_icache(void);
81void flush_icache(void); 82void flush_icache(void);
82#endif 83#endif
83 84
84#else
85unsigned int current_core(void);
86#endif /* CPU_PP502x */ 85#endif /* CPU_PP502x */
87 86
88 87