diff options
Diffstat (limited to 'firmware/target/arm/system-pp5002.c')
-rw-r--r-- | firmware/target/arm/system-pp5002.c | 71 |
1 files changed, 55 insertions, 16 deletions
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c index 08783280be..164913f0f6 100644 --- a/firmware/target/arm/system-pp5002.c +++ b/firmware/target/arm/system-pp5002.c | |||
@@ -44,9 +44,7 @@ void irq(void) | |||
44 | } | 44 | } |
45 | else | 45 | else |
46 | { | 46 | { |
47 | if (COP_INT_STAT & TIMER1_MASK) | 47 | if (COP_INT_STAT & TIMER2_MASK) |
48 | TIMER1(); | ||
49 | else if (COP_INT_STAT & TIMER2_MASK) | ||
50 | TIMER2(); | 48 | TIMER2(); |
51 | } | 49 | } |
52 | } | 50 | } |
@@ -61,24 +59,60 @@ void irq(void) | |||
61 | some other CPU frequency scaling. */ | 59 | some other CPU frequency scaling. */ |
62 | 60 | ||
63 | #ifndef BOOTLOADER | 61 | #ifndef BOOTLOADER |
62 | void flush_icache(void) ICODE_ATTR; | ||
63 | void flush_icache(void) | ||
64 | { | ||
65 | intptr_t b, e; | ||
66 | |||
67 | for (b = (intptr_t)&CACHE_FLUSH_BASE, e = b + CACHE_SIZE; | ||
68 | b < e; b += 16) { | ||
69 | outl(0x0, b); | ||
70 | } | ||
71 | } | ||
72 | |||
73 | void invalidate_icache(void) ICODE_ATTR; | ||
74 | void invalidate_icache(void) | ||
75 | { | ||
76 | intptr_t b, e; | ||
77 | |||
78 | /* Flush */ | ||
79 | for (b = (intptr_t)&CACHE_FLUSH_BASE, e = b + CACHE_SIZE; | ||
80 | b < e; b += 16) { | ||
81 | outl(0x0, b); | ||
82 | } | ||
83 | |||
84 | /* Invalidate */ | ||
85 | for (b = (intptr_t)&CACHE_INVALIDATE_BASE, e = b + CACHE_SIZE; | ||
86 | b < e; b += 16) { | ||
87 | outl(0x0, b); | ||
88 | } | ||
89 | } | ||
90 | |||
64 | static void ipod_init_cache(void) | 91 | static void ipod_init_cache(void) |
65 | { | 92 | { |
66 | int i =0; | 93 | intptr_t b, e; |
94 | |||
67 | /* Initialising the cache in the iPod bootloader prevents Rockbox from starting */ | 95 | /* Initialising the cache in the iPod bootloader prevents Rockbox from starting */ |
68 | outl(inl(0xcf004050) & ~0x700, 0xcf004050); | 96 | PROC_STAT &= ~0x700; |
69 | outl(0x4000, 0xcf004020); | 97 | outl(0x4000, 0xcf004020); |
70 | 98 | ||
71 | outl(0x2, 0xcf004024); | 99 | CACHE_CTL = CACHE_INIT; |
72 | 100 | ||
73 | /* PP5002 has 8KB cache */ | 101 | for (b = (intptr_t)&CACHE_INVALIDATE_BASE, e = b + CACHE_SIZE; |
74 | for (i = 0xf0004000; i < (int)(0xf0006000); i += 16) { | 102 | b < e; b += 16) { |
75 | outl(0x0, i); | 103 | outl(0x0, b); |
76 | } | 104 | } |
77 | 105 | ||
78 | outl(0x0, 0xf000f020); | 106 | /* Cache if (addr & mask) >> 16 == (mask & match) >> 16: |
79 | outl(0x3fc0, 0xf000f024); | 107 | * yes: 0x00000000 - 0x03ffffff |
108 | * no: 0x04000000 - 0x1fffffff | ||
109 | * yes: 0x20000000 - 0x23ffffff | ||
110 | * no: 0x24000000 - 0x3fffffff <= range containing uncached alias | ||
111 | */ | ||
112 | CACHE_MASK = 0x00001c00; | ||
113 | CACHE_OPERATION = 0x3fc0; | ||
80 | 114 | ||
81 | outl(0x3, 0xcf004024); | 115 | CACHE_CTL = CACHE_INIT | CACHE_RUN; |
82 | } | 116 | } |
83 | 117 | ||
84 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 118 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |
@@ -132,9 +166,10 @@ void system_init(void) | |||
132 | #ifndef BOOTLOADER | 166 | #ifndef BOOTLOADER |
133 | if (CURRENT_CORE == CPU) | 167 | if (CURRENT_CORE == CPU) |
134 | { | 168 | { |
135 | /* Remap the flash ROM from 0x00000000 to 0x20000000. */ | 169 | /* Remap the flash ROM on CPU, keep hidden from COP: |
136 | MMAP3_LOGICAL = 0x20000000 | 0x3a00; | 170 | * 0x00000000-0x03ffffff = 0x20000000-0x23ffffff */ |
137 | MMAP3_PHYSICAL = 0x00000000 | 0x3f84; | 171 | MMAP1_LOGICAL = 0x20003c00; |
172 | MMAP1_PHYSICAL = 0x00003f84; | ||
138 | 173 | ||
139 | #if defined(IPOD_1G2G) || defined(IPOD_3G) | 174 | #if defined(IPOD_1G2G) || defined(IPOD_3G) |
140 | DEV_EN = 0x0b9f; /* don't clock unused PP5002 hardware components */ | 175 | DEV_EN = 0x0b9f; /* don't clock unused PP5002 hardware components */ |
@@ -150,7 +185,11 @@ void system_init(void) | |||
150 | GPIOC_INT_EN = 0; | 185 | GPIOC_INT_EN = 0; |
151 | GPIOD_INT_EN = 0; | 186 | GPIOD_INT_EN = 0; |
152 | 187 | ||
153 | #ifndef HAVE_ADJUSTABLE_CPU_FREQ | 188 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |
189 | #if NUM_CORES > 1 | ||
190 | cpu_boost_init(); | ||
191 | #endif | ||
192 | #else | ||
154 | pp_set_cpu_frequency(CPUFREQ_MAX); | 193 | pp_set_cpu_frequency(CPUFREQ_MAX); |
155 | #endif | 194 | #endif |
156 | } | 195 | } |