1 files changed, 170 insertions, 6 deletions

diff --git a/firmware/target/arm/s5l8702/pcm-s5l8702.c b/firmware/target/arm/s5l8702/pcm-s5l8702.c
index a4ea56edce..446be24008 100644
--- a/firmware/target/arm/s5l8702/pcm-s5l8702.c
+++ b/firmware/target/arm/s5l8702/pcm-s5l8702.c
@@ -250,37 +250,201 @@ void * pcm_dma_addr(void *addr)
  ** Recording DMA transfer
  **/
 #ifdef HAVE_RECORDING
+static volatile int rec_locked = 0;
+static void *rec_dma_addr;
+static size_t rec_dma_size;
+static bool pcm_rec_initialized = false;
+static int completed_task;
+
+/* ahead capture buffer */
+#define PCM_AHEADBUF_SAMPLES    128
+#define AHEADBUF_SZ             (PCM_AHEADBUF_SAMPLES * 4)
+static unsigned char ahead_buf[AHEADBUF_SZ] CACHEALIGN_ATTR;
+
+/* DMA configuration */
+static void dma_rec_callback(void *cb_data) ICODE_ATTR;
+
+enum {  /* cb_data */
+    TASK_AHEADBUF,
+    TASK_RECBUF
+};
+
+#define DMA_REC_TSKBUF_SZ   2   /* N tasks, MUST be pow2 */
+#define DMA_REC_LLIBUF_SZ   8   /* N LLIs, MUST be pow2 */
+static struct dmac_tsk dma_rec_tskbuf[DMA_REC_TSKBUF_SZ];
+static struct dmac_lli volatile \
+            dma_rec_llibuf[DMA_REC_LLIBUF_SZ] CACHEALIGN_ATTR;
+
+static struct dmac_ch dma_rec_ch = {
+    .dmac = &s5l8702_dmac0,
+    .prio = DMAC_CH_PRIO(1),
+    .cb_fn = dma_rec_callback,
+
+    .llibuf = dma_rec_llibuf,
+    .llibuf_mask = DMA_REC_LLIBUF_SZ - 1,
+    .llibuf_bus = DMAC_MASTER_AHB1,
+
+    .tskbuf = dma_rec_tskbuf,
+    .tskbuf_mask = DMA_REC_TSKBUF_SZ - 1,
+    .queue_mode = QUEUE_LINK,
+};
+
+static struct dmac_ch_cfg dma_rec_ch_cfg = {
+    .srcperi = S5L8702_DMAC0_PERI_IIS0_RX,
+    .dstperi = S5L8702_DMAC0_PERI_MEM,
+    .sbsize  = DMACCxCONTROL_BSIZE_4,
+    .dbsize  = DMACCxCONTROL_BSIZE_4,
+    .swidth  = DMACCxCONTROL_WIDTH_16,
+    .dwidth  = DMACCxCONTROL_WIDTH_16,
+    .sbus    = DMAC_MASTER_AHB1,
+    .dbus    = DMAC_MASTER_AHB1,
+    .sinc    = DMACCxCONTROL_INC_DISABLE,
+    .dinc    = DMACCxCONTROL_INC_ENABLE,
+    .prot    = DMAC_PROT_CACH | DMAC_PROT_BUFF | DMAC_PROT_PRIV,
+    /* align LLI transfers to L-R pairs (samples) */
+    .lli_xfer_max_count = DMAC_LLI_MAX_COUNT & ~1,
+};
+
+/* maximum and minimum supported block sizes in bytes */
+#define MIN_SIZE ((size_t) (AHEADBUF_SZ * 2))
+#define MAX_SIZE ((size_t) (AHEADBUF_SZ + ((DMA_REC_LLIBUF_SZ - 1) * \
+             (dma_rec_ch_cfg.lli_xfer_max_count << dma_rec_ch_cfg.swidth))))
+
+#if 0
+#define SIZE_PANIC(sz) { \
+    if (((sz) < MIN_SIZE) || ((sz) > MAX_SIZE)) \
+        panicf("pcm record: unsupported size: %d", (sz)); \
+}
+#else
+#define SIZE_PANIC(sz) {}
+#endif
+
+
+static void rec_dmac_ch_queue(void *addr, size_t size, int cb_data)
+{
+    discard_dcache_range(addr, size);
+    dmac_ch_queue(&dma_rec_ch, (void*)S5L8702_DADDR_PERI_IIS0_RX,
+                                            addr, size, (void *)cb_data);
+}
+
+static void dma_rec_callback(void *cb_data)
+{
+    completed_task = (int)cb_data;
+
+    if (completed_task == TASK_AHEADBUF)
+    {
+        /* safety check */
+        if (rec_dma_addr == NULL)
+            return; /* capture finished */
+
+        /* move ahead buffer to record buffer and queue
+           next capture-ahead task */
+        memcpy(rec_dma_addr, ahead_buf, AHEADBUF_SZ);
+        rec_dmac_ch_queue(ahead_buf, AHEADBUF_SZ, TASK_AHEADBUF);
+    }
+    else /* TASK_RECBUF */
+    {
+        /* Inform middle layer */
+        if (pcm_rec_dma_complete_callback(
+                    PCM_DMAST_OK, &rec_dma_addr, &rec_dma_size))
+        {
+            SIZE_PANIC(rec_dma_size);
+            rec_dmac_ch_queue(rec_dma_addr + AHEADBUF_SZ,
+                        rec_dma_size - AHEADBUF_SZ, TASK_RECBUF);
+            pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
+        }
+    }
+}
+
 void pcm_rec_lock(void)
 {
+    if ((rec_locked++ == 0) && pcm_rec_initialized)
+        dmac_ch_lock_int(&dma_rec_ch);
 }
 
 void pcm_rec_unlock(void)
 {
+    if ((--rec_locked == 0) && pcm_rec_initialized)
+        dmac_ch_unlock_int(&dma_rec_ch);
 }
 
 void pcm_rec_dma_stop(void)
 {
+    if (!pcm_rec_initialized)
+        return;
+
+    dmac_ch_stop(&dma_rec_ch);
+
+    I2SRXCOM = 0x2; /* stop Rx I2S */
 }
 
 void pcm_rec_dma_start(void *addr, size_t size)
 {
-    (void)addr;
-    (void)size;
+    SIZE_PANIC(size);
+
+    pcm_rec_dma_stop();
+
+    rec_dma_addr = addr;
+    rec_dma_size = size;
+    completed_task = -1;
+
+    /* launch first DMA transfer to capture into ahead buffer,
+       link the second task to capture into record buffer */
+    rec_dmac_ch_queue(ahead_buf, AHEADBUF_SZ, TASK_AHEADBUF);
+    rec_dmac_ch_queue(addr + AHEADBUF_SZ, size - AHEADBUF_SZ, TASK_RECBUF);
+
+    I2SRXCOM = 0x6; /* start Rx I2S */
 }
 
 void pcm_rec_dma_close(void)
 {
+    pcm_rec_dma_stop();
 }
 
-
 void pcm_rec_dma_init(void)
 {
-}
+    if (pcm_rec_initialized)
+        return;
 
+    PWRCON(0) &= ~(1 << 4);
+    PWRCON(0) &= ~(1 << 7);
+
+    dmac_ch_init(&dma_rec_ch, &dma_rec_ch_cfg);
+
+    /* synchronize lock status */
+    if (rec_locked)
+        dmac_ch_lock_int(&dma_rec_ch);
+
+    I2SRXCON = 0x1000;
+    I2SCLKCON = 1;
+
+    pcm_rec_initialized = true;
+}
 
 const void * pcm_rec_dma_get_peak_buffer(void)
 {
-    return NULL;
-}
+    void *dstaddr;
+
+    pcm_rec_lock();
 
+    if (completed_task == TASK_AHEADBUF) {
+        dstaddr = dmac_ch_get_info(&dma_rec_ch, NULL, NULL);
+
+        if ((dstaddr < rec_dma_addr) ||
+                    (dstaddr > rec_dma_addr + rec_dma_size))
+            /* At this moment, interrupt for TASK_RECBUF is waiting to
+               be handled. TASK_RECBUF is already finished and HW is
+               transfering next TASK_AHEADBUF. Return whole block. */
+            dstaddr = rec_dma_addr + rec_dma_size;
+    }
+    else {
+        /* Ahead buffer not yet captured _and_ moved to
+           record buffer. Return nothing. */
+        dstaddr = rec_dma_addr;
+    }
+
+    pcm_rec_unlock();
+
+    return CACHEALIGN_DOWN(dstaddr);
+}
 #endif /* HAVE_RECORDING */