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Diffstat (limited to 'firmware/target/arm/s5l8700')
-rw-r--r--firmware/target/arm/s5l8700/boot.lds23
-rw-r--r--firmware/target/arm/s5l8700/crt0.S8
2 files changed, 20 insertions, 11 deletions
diff --git a/firmware/target/arm/s5l8700/boot.lds b/firmware/target/arm/s5l8700/boot.lds
index 4fe59b79ed..ccedda579d 100644
--- a/firmware/target/arm/s5l8700/boot.lds
+++ b/firmware/target/arm/s5l8700/boot.lds
@@ -9,8 +9,13 @@ OUTPUT_FORMAT(elf32-bigarm)
9OUTPUT_ARCH(arm) 9OUTPUT_ARCH(arm)
10STARTUP(target/arm/s5l8700/crt0.o) 10STARTUP(target/arm/s5l8700/crt0.o)
11 11
12#ifdef IPOD_NANO2G
13#define DRAMORIG 0x08000000 + ((MEMORYSIZE - 1) * 0x100000)
14#define DRAMSIZE 0x00100000
15#else
12#define DRAMORIG 0x08000000 16#define DRAMORIG 0x08000000
13#define DRAMSIZE (MEMORYSIZE * 0x100000) 17#define DRAMSIZE (MEMORYSIZE * 0x100000)
18#endif
14 19
15#define IRAMORIG 0x22000000 20#define IRAMORIG 0x22000000
16#if CONFIG_CPU==S5L8701 21#if CONFIG_CPU==S5L8701
@@ -39,19 +44,25 @@ MEMORY
39#if defined(IPOD_NANO2G) || defined(MEIZU_M6SL) 44#if defined(IPOD_NANO2G) || defined(MEIZU_M6SL)
40#define LOAD_AREA IRAM 45#define LOAD_AREA IRAM
41#else 46#else
47#define NEEDS_INTVECT_COPYING
42#define LOAD_AREA FLASH 48#define LOAD_AREA FLASH
43#endif 49#endif
44 50
45SECTIONS 51SECTIONS
46{ 52{
53#ifdef NEEDS_INTVECT_COPYING
47 .intvect : { 54 .intvect : {
48 _intvectstart = . ; 55 _intvectstart = . ;
49 *(.intvect) 56 *(.intvect)
50 _intvectend = _newstart ; 57 _intvectend = _newstart ;
51 } >IRAM AT> LOAD_AREA 58 } >IRAM AT> LOAD_AREA
52 _intvectcopy = LOADADDR(.intvect) ; 59 _intvectcopy = LOADADDR(.intvect) ;
60#endif
53 61
54 .text : { 62 .text : {
63#ifndef NEEDS_INTVECT_COPYING
64 *(.intvect)
65#endif
55 *(.init.text) 66 *(.init.text)
56 *(.text*) 67 *(.text*)
57 *(.glue_7*) 68 *(.glue_7*)
@@ -90,12 +101,8 @@ SECTIONS
90 _fiqstackend = .; 101 _fiqstackend = .;
91 } > IRAM 102 } > IRAM
92 103
93 . = DRAMORIG; 104 /* The bss section is too large for IRAM on the Nano 2G, thanks to the FTL.
94#ifdef IPOD_NANO2G 105 We just move it 31MB into the DRAM */
95 /* The bss section is too large for IRAM - we just move it 12MB into the
96 DRAM */
97 . += (12*1024*1024);
98#endif
99 .bss (NOLOAD) : { 106 .bss (NOLOAD) : {
100 _edata = .; 107 _edata = .;
101 *(.bss*); 108 *(.bss*);
@@ -104,5 +111,9 @@ SECTIONS
104 *(COMMON); 111 *(COMMON);
105 . = ALIGN(0x4); 112 . = ALIGN(0x4);
106 _end = .; 113 _end = .;
114#ifdef IPOD_NANO2G
107 } > DRAM 115 } > DRAM
116#else
117 } > IRAM
118#endif
108} 119}
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S
index 583b762505..5fd959cf91 100644
--- a/firmware/target/arm/s5l8700/crt0.S
+++ b/firmware/target/arm/s5l8700/crt0.S
@@ -49,11 +49,7 @@
49 .global _newstart 49 .global _newstart
50 /* Exception vectors */ 50 /* Exception vectors */
51start: 51start:
52#if CONFIG_CPU==S5L8701 && defined(BOOTLOADER)
53 b newstart2
54#else
55 b _newstart 52 b _newstart
56#endif
57 ldr pc, =undef_instr_handler 53 ldr pc, =undef_instr_handler
58 ldr pc, =software_int_handler 54 ldr pc, =software_int_handler
59 ldr pc, =prefetch_abort_handler 55 ldr pc, =prefetch_abort_handler
@@ -66,9 +62,11 @@ start:
66#endif 62#endif
67 .ltorg 63 .ltorg
68_newstart: 64_newstart:
65#if CONFIG_CPU!=S5L8701 || !defined(BOOTLOADER)
69 ldr pc, =newstart2 // we do not want to execute from 0x0 as iram will be mapped there 66 ldr pc, =newstart2 // we do not want to execute from 0x0 as iram will be mapped there
70 .section .init.text,"ax",%progbits 67 .section .init.text,"ax",%progbits
71newstart2: 68newstart2:
69#endif
72 msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ 70 msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
73 71
74#ifdef ROCKBOX_BIG_ENDIAN 72#ifdef ROCKBOX_BIG_ENDIAN
@@ -77,7 +75,7 @@ newstart2:
77 orr r0, r0, r1 75 orr r0, r0, r1
78 mcr 15, 0, r0, c1, c0, 0 // set bigendian 76 mcr 15, 0, r0, c1, c0, 0 // set bigendian
79#endif 77#endif
80 78
81 ldr r1, =0x3c800000 // disable watchdog 79 ldr r1, =0x3c800000 // disable watchdog
82 mov r0, #0xa5 80 mov r0, #0xa5
83 str r0, [r1] 81 str r0, [r1]