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Diffstat (limited to 'firmware/target/arm/s5l8700')
-rw-r--r--firmware/target/arm/s5l8700/boot.lds2
-rw-r--r--firmware/target/arm/s5l8700/crt0.S69
2 files changed, 66 insertions, 5 deletions
diff --git a/firmware/target/arm/s5l8700/boot.lds b/firmware/target/arm/s5l8700/boot.lds
index 6f43177c86..ba5a4a4cac 100644
--- a/firmware/target/arm/s5l8700/boot.lds
+++ b/firmware/target/arm/s5l8700/boot.lds
@@ -104,7 +104,7 @@ SECTIONS
104 *(COMMON); 104 *(COMMON);
105 . = ALIGN(0x4); 105 . = ALIGN(0x4);
106 _end = .; 106 _end = .;
107#ifdef IPOD_NANO2G 107#if defined(IPOD_NANO2G) || defined(MEIZU_M6SP)
108 } > DRAM 108 } > DRAM
109#else /* other targets don't have DRAM set up yet */ 109#else /* other targets don't have DRAM set up yet */
110 } > IRAM 110 } > IRAM
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S
index 4904c18dd3..5faaf4e834 100644
--- a/firmware/target/arm/s5l8700/crt0.S
+++ b/firmware/target/arm/s5l8700/crt0.S
@@ -55,7 +55,7 @@ newstart2:
55 orr r0, r0, r1 55 orr r0, r0, r1
56 mcr 15, 0, r0, c1, c0, 0 // set bigendian 56 mcr 15, 0, r0, c1, c0, 0 // set bigendian
57#endif 57#endif
58 58
59 ldr r1, =0x3c800000 // disable watchdog 59 ldr r1, =0x3c800000 // disable watchdog
60 mov r0, #0xa5 60 mov r0, #0xa5
61 str r0, [r1] 61 str r0, [r1]
@@ -107,7 +107,7 @@ start_loc:
107#if !(CONFIG_CPU==S5L8701 && defined(BOOTLOADER)) 107#if !(CONFIG_CPU==S5L8701 && defined(BOOTLOADER))
108 ldr r1, =0x3c500000 108 ldr r1, =0x3c500000
109 ldr r0, =0x00800080 109 ldr r0, =0x00800080
110 str r0, [r1] // CLKCON 110 str r0, [r1] // CLKCON
111 mov r0, #0 111 mov r0, #0
112 str r0, [r1,#0x24] // PLLCON 112 str r0, [r1,#0x24] // PLLCON
113#ifdef IPOD_NANO2G 113#ifdef IPOD_NANO2G
@@ -136,7 +136,7 @@ start_loc:
136 orr r0, r0, r2 136 orr r0, r0, r2
137 mcr 15, 0, r0, c1, c0, 0 // asynchronous clocking mode 137 mcr 15, 0, r0, c1, c0, 0 // asynchronous clocking mode
138 nop 138 nop
139 nop 139 nop
140 nop 140 nop
141 nop 141 nop
142#endif 142#endif
@@ -236,6 +236,67 @@ start_loc:
236 mov r0, #0 // 0x0 236 mov r0, #0 // 0x0
237 str r0, [r1, #44] // do not enter any power saving mode 237 str r0, [r1, #44] // do not enter any power saving mode
238 238
239#ifdef MEIZU_M6SP
240 /* setup SDRAM for Meizu M6SP */
241 ldr r1, =0x38200000
242 // configure SDR drive strength and pad settings
243 mov r0, #5
244 str r0, [r1, #0x4C] // MIU_DSS_SEL_B
245 mov r0, #2
246 str r0, [r1, #0x50] // MIU_DSS_SEL_O
247 str r0, [r1, #0x54] // MIU_DSS_SEL_C
248 mov r0, #2
249 str r0, [r1, #0x60] // SSTL2_PAD_ON
250 // select SDR mode
251 ldr r0, [r1, #0x40]
252 mov r2, #0xFFFDFFFF
253 and r0, r0, r2
254 orr r0, r0, #1
255 str r0, [r1, #0x40] // MIUORG
256 // set controller configuration
257 mov r0, #0x700
258 str r0, [r1] // MIUCON
259 // set SDRAM timing
260 ldr r0, =0x6A4965
261 str r0, [r1, #0x10] // MIUSDPARA
262 // set refresh rate
263 mov r0, #0x1080
264 str r0, [r1, #0x08] // MIUAREF
265 // initialise SDRAM
266 mov r0, #0x003
267 str r0, [r1, #0x04] // MIUCOM = nop
268 ldr r0, =0x203
269 str r0, [r1, #0x04] // MIUCOM = precharge all banks
270 nop
271 nop
272 nop
273 ldr r0, =0x303
274 str r0, [r1, #0x04] // MIUCOM = auto-refresh
275 nop
276 nop
277 nop
278 nop
279 str r0, [r1, #0x04] // MIUCOM = auto-refresh
280 nop
281 nop
282 nop
283 nop
284 str r0, [r1, #0x04] // MIUCOM = auto-refresh
285 nop
286 nop
287 nop
288 nop
289 // set mode register
290 mov r0, #0x33
291 str r0, [r1, #0x0C] // MIUMRS
292 ldr r0, =0x103
293 str r0, [r1, #0x04] // MIUCOM = mode register set
294 ldr r0, =0x4033
295 str r0, [r1, #0x0C] // MIUMRS
296 ldr r0, =0x103
297 str r0, [r1, #0x04] // MIUCOM = mode register set
298#endif /* MEIZU_M6SP */
299
239 mov r1, #0x1 300 mov r1, #0x1
240 mrc 15, 0, r0, c1, c0, 0 301 mrc 15, 0, r0, c1, c0, 0
241 bic r0, r0, r1 302 bic r0, r0, r1
@@ -364,7 +425,7 @@ start_loc:
364 ldrhi r1, [r4], #4 425 ldrhi r1, [r4], #4
365 strhi r1, [r2], #4 426 strhi r1, [r2], #4
366 bhi 1b 427 bhi 1b
367 428
368 /* Initialise ibss section to zero */ 429 /* Initialise ibss section to zero */
369 ldr r2, =_iedata 430 ldr r2, =_iedata
370 ldr r3, =_iend 431 ldr r3, =_iend