diff options
Diffstat (limited to 'firmware/target/arm/s5l8700/mmu-s5l8700.S')
-rw-r--r-- | firmware/target/arm/s5l8700/mmu-s5l8700.S | 95 |
1 files changed, 0 insertions, 95 deletions
diff --git a/firmware/target/arm/s5l8700/mmu-s5l8700.S b/firmware/target/arm/s5l8700/mmu-s5l8700.S deleted file mode 100644 index 35406b9c5c..0000000000 --- a/firmware/target/arm/s5l8700/mmu-s5l8700.S +++ /dev/null | |||
@@ -1,95 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006,2007 by Greg White | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "cpu.h" | ||
23 | |||
24 | /** Cache coherency **/ | ||
25 | |||
26 | /* | ||
27 | * Cleans entire DCache | ||
28 | * void clean_dcache(void); | ||
29 | */ | ||
30 | .section .icode, "ax", %progbits | ||
31 | .align 2 | ||
32 | .global clean_dcache | ||
33 | .type clean_dcache, %function | ||
34 | .global cpucache_flush @ Alias | ||
35 | clean_dcache: | ||
36 | cpucache_flush: | ||
37 | @ Index format: 31:26 = index, 5:4 = segment, remainder = SBZ | ||
38 | mov r1, #0x00000000 @ | ||
39 | 1: @ clean_start @ | ||
40 | mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index | ||
41 | add r0, r1, #0x00000010 @ | ||
42 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | ||
43 | add r0, r0, #0x00000010 @ | ||
44 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | ||
45 | add r0, r0, #0x00000010 @ | ||
46 | mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index | ||
47 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end | ||
48 | bne 1b @ clean_start @ | ||
49 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer | ||
50 | bx lr @ | ||
51 | .size clean_dcache, .-clean_dcache | ||
52 | |||
53 | /* | ||
54 | * Invalidate entire DCache | ||
55 | * will do writeback | ||
56 | * void invalidate_dcache(void); | ||
57 | */ | ||
58 | .section .icode, "ax", %progbits | ||
59 | .align 2 | ||
60 | .global invalidate_dcache | ||
61 | .type invalidate_dcache, %function | ||
62 | invalidate_dcache: | ||
63 | @ Index format: 31:26 = index, 5:4 = segment, remainder = SBZ | ||
64 | mov r1, #0x00000000 @ | ||
65 | 1: @ inv_start @ | ||
66 | mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index | ||
67 | add r0, r1, #0x00000010 @ | ||
68 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index | ||
69 | add r0, r0, #0x00000010 @ | ||
70 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index | ||
71 | add r0, r0, #0x00000010 @ | ||
72 | mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index | ||
73 | adds r1, r1, #0x04000000 @ will wrap to zero at loop end | ||
74 | bne 1b @ inv_start @ | ||
75 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer | ||
76 | bx lr @ | ||
77 | .size invalidate_dcache, .-invalidate_dcache | ||
78 | |||
79 | /* | ||
80 | * Invalidate entire ICache and DCache | ||
81 | * will do writeback | ||
82 | * void invalidate_idcache(void); | ||
83 | */ | ||
84 | .section .icode, "ax", %progbits | ||
85 | .align 2 | ||
86 | .global invalidate_idcache | ||
87 | .type invalidate_idcache, %function | ||
88 | .global cpucache_invalidate @ Alias | ||
89 | invalidate_idcache: | ||
90 | cpucache_invalidate: | ||
91 | mov r2, lr @ save lr to r2, call uses r0 and r1 only | ||
92 | bl invalidate_dcache @ Clean and invalidate entire DCache | ||
93 | mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call) | ||
94 | mov pc, r2 @ | ||
95 | .size invalidate_idcache, .-invalidate_idcache | ||