1 files changed, 320 insertions, 0 deletions
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S
new file mode 100644
index 0000000000..0dcc203844
--- /dev/null
+++ b/firmware/target/arm/s5l8700/crt0.S
@@ -0,0 +1,320 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: crt0.S 18776 2008-10-11 18:32:17Z gevaerts $
+ *
+ * Copyright (C) 2008 by Marcoen Hirschberg
+ * Copyright (C) 2008 by Denes Balatoni
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "cpu.h"
+    .section .intvect,"ax",%progbits
+    .global    _start
+    .global    _newstart
+    /* Exception vectors */
+_start:
+    b _newstart
+    ldr pc, =undef_instr_handler
+    ldr pc, =software_int_handler
+    ldr pc, =prefetch_abort_handler
+    ldr pc, =data_abort_handler
+    ldr pc, =reserved_handler
+    ldr pc, =irq_handler
+    ldr pc, =fiq_handler
+#if CONFIG_CPU==S5L8700
+    .word 0x43554644 /* DFUC */
+#endif
+    .ltorg
+_newstart:
+    ldr pc, =newstart2 // we do not want to execute from 0x0 as iram will be mapped there
+    .section .init.text,"ax",%progbits
+newstart2:
+    msr     cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
+    mov r1, #0x80
+    mrc 15, 0, r0, c1, c0, 0
+    orr r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // set bigendian
+                         
+    ldr r1, =0x3c800000 // disable watchdog
+    mov r0, #0xa5
+    str r0, [r1]
+    mov r0, #0
+    ldr r1, =0x39c00008
+    str r0, [r1] // mask all interrupts
+    ldr r1, =0x39c00020
+    str r0, [r1] // mask all external interrupts
+    mvn r0, #0
+    mov r1, #0x39c00000
+    str r0, [r1] // irq priority
+    ldr r1, =0x39c00010
+    str r0, [r1] // clear pending interrupts
+    ldr r1, =0x39c0001c
+    str r0, [r1] // clear pending external interrupts
+                                                                            
+//    ldr r1, =0x3cf00000
+//    ldr r0, [r1]
+//    mvn r2, #0x30
+//    and r0, r0, r2
+//    mov r2, #0x10
+//    orr r0, r0, r2
+//    str r0, [r1]
+//    ldr r1, =0x3cf00004
+//    ldr r0, [r1]
+//    mov r2, #4
+//    orr r0, r0, r2
+//    str r0, [r1] // switch backlight on
+    ldr r1, =0x3c500000 // CLKCON
+    ldr r0, =0x00800080
+    str r0, [r1]
+    ldr r1, =0x3c500024 // PLLCON
+    mov r0, #0
+    str r0, [r1]
+    ldr r1, =0x3c500004 // PLL0PMS
+    ldr r0, =0x1ad200
+    str r0, [r1]
+    ldr r1, =0x3c500014 // PLL0LCNT
+    ldr r0, =8100
+    str r0, [r1]
+    ldr r1, =0x3c500024 // PLLCON
+    mov r0, #1
+    str r0, [r1]
+    ldr r1, =0x3c500020 // PLLLOCK
+1:
+    ldr r0, [r1]
+    tst r0, #1
+    beq 1b
+    ldr r1, =0x3c50003c // CLKCON2
+    mov r0, #0x80
+    str r0, [r1]
+    ldr r1, =0x3c500000 // CLKCON
+    ldr r0, =0x20803180
+    str r0, [r1] // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
+    ldr r2, =0xc0000078
+    mrc 15, 0, r0, c1, c0, 0
+    mvn r1, #0xc0000000
+    and r0, r0, r1
+    orr r0, r0, r2
+    mcr 15, 0, r0, c1, c0, 0 // asynchronous clocking mode
+    nop
+    nop                                         
+    nop
+    nop
+//    ldr r0, =0x10100000
+//    ldr r1, =0x38200034
+//    str r0, [r1] // SRAM0/1 data width 16 bit
+//    ldr r0, =0x00220922
+//    ldr r7, =0x38200038
+//    str r0, [r7] // SRAM0/1 clocks
+//    ldr r0, =0x00220922
+//    ldr r9, =0x3820003c
+//    str r0, [r9] // SRAM2/3 clocks
+//    nop
+//    nop
+//    nop
+//    nop
+    ldr r1, =0x3c500000
+    mov r0, #0  // 0x0
+    str r0, [r1, #40] // enable clock for all peripherals
+    mov r0, #0  // 0x0
+    str r0, [r1, #44] // do not enter any power saving mode
+    mov r1, #0x1
+    mrc 15, 0, r0, c1, c0, 0
+    bic r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // disable protection unit
+    mov r1, #0x4
+    mrc 15, 0, r0, c1, c0, 0
+    bic r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // dcache disable
+    mov r1, #0x1000
+    mrc 15, 0, r0, c1, c0, 0
+    bic r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // icache disable
+    mov r1, #0
+1:
+    mov r0, #0
+2:
+    orr r2, r1, r0
+    mcr 15, 0, r2, c7, c14, 2 // clean and flush dcache single entry
+    add r0, r0, #0x10
+    cmp r0, #0x40
+    bne 2b
+    add r1, r1, #0x4000000
+    cmp r1, #0x0
+    bne 1b
+    nop
+    nop
+    mov r0, #0
+    mcr 15, 0, r0, c7, c10, 4 // clean and flush whole dcache
+                                                                            
+    mov r0, #0
+    mcr 15, 0, r0, c7, c5, 0 // flush icache
+    
+    mov r0, #0
+    mcr 15, 0, r0, c7, c6, 0 // flush dcache
+                               
+    mov r0, #0x3f
+    mcr 15, 0, r0, c6, c0, 1
+    mov r0, #0x2f
+    mcr 15, 0, r0, c6, c1, 1
+    ldr r0, =0x0800002f
+    mcr 15, 0, r0, c6, c2, 1
+    ldr r0, =0x22000023
+    mcr 15, 0, r0, c6, c3, 1
+    ldr r0, =0x24000027
+    mcr 15, 0, r0, c6, c4, 1
+    mov r0, #0x3f
+    mcr 15, 0, r0, c6, c0, 0
+    mov r0, #0x2f
+    mcr 15, 0, r0, c6, c1, 0
+    ldr r0, =0x0800002f
+    mcr 15, 0, r0, c6, c2, 0
+    ldr r0, =0x22000023
+    mcr 15, 0, r0, c6, c3, 0
+    ldr r0, =0x24000029
+    mcr 15, 0, r0, c6, c4, 0
+    mov r0, #0x1e
+    mcr 15, 0, r0, c2, c0, 1
+    mov r0, #0x1e
+    mcr 15, 0, r0, c2, c0, 0
+    mov r0, #0x1e
+    mcr 15, 0, r0, c3, c0, 0
+    ldr r0, =0x0000ffff
+    mcr 15, 0, r0, c5, c0, 1
+    ldr r0, =0x0000ffff
+    mcr 15, 0, r0, c5, c0, 0 // set up protection and caching
+                                                                        
+    mov r1, #0x4
+    mrc 15, 0, r0, c1, c0, 0
+    orr r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // dcache enable
+    
+    mov r1, #0x1000
+    mrc 15, 0, r0, c1, c0, 0
+    orr r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // icache enable
+                                                   
+    mov r1, #0x1
+    mrc 15, 0, r0, c1, c0, 0
+    orr r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // enable protection unit
+    
+    /* Copy interrupt vectors to iram */
+    ldr     r2, =_intvectstart
+    ldr     r3, =_intvectend
+    ldr     r4, =_intvectcopy
+1:
+    cmp     r3, r2
+    ldrhi   r1, [r4], #4
+    strhi   r1, [r2], #4
+    bhi     1b
+    /* Initialise bss section to zero */
+    ldr     r2, =_edata
+    ldr     r3, =_end
+    mov     r4, #0
+1:
+    cmp     r3, r2
+    strhi   r4, [r2], #4
+    bhi     1b
+     
+    /* Copy icode and data to ram */
+    ldr     r2, =_datastart
+    ldr     r3, =_dataend
+    ldr     r4, =_datacopy
+1:
+    cmp     r3, r2
+    ldrhi   r1, [r4], #4
+    strhi   r1, [r2], #4
+    bhi     1b
+    
+    /* Set up some stack and munge it with 0xdeadbeef */
+    ldr     sp, =_stackend
+    ldr     r2, =_stackbegin
+    ldr     r3, =0xdeadbeef
+1:
+    cmp     sp, r2
+    strhi   r3, [r2], #4
+    bhi     1b
+    
+    /* Set up stack for IRQ mode */ 
+    msr     cpsr_c, #0xd2
+    ldr     sp, =_irqstackend
+    /* Set up stack for FIQ mode */ 
+    msr     cpsr_c, #0xd1
+    ldr     sp, =_fiqstackend
+    /* Let abort and undefined modes use IRQ stack */
+    msr     cpsr_c, #0xd7
+    ldr     sp, =_irqstackend
+    msr     cpsr_c, #0xdb
+    ldr     sp, =_irqstackend
+    /* Switch back to supervisor mode */
+    msr     cpsr_c, #0xd3
+// if we did not switch remap on, device
+// would crash when MENU is pressed,
+// as that button is connected to BOOT_MODE pin
+    ldr r1, =0x38200000
+    ldr r0, [r1]
+    mvn r2, #0x10000
+    and r0, r0, r2
+    mov r2, #0x1
+    orr r0, r0, r2
+    str r0, [r1] // remap iram to address 0x0
+    bl      main
+    .text
+/*    .global UIE*/
+/* All illegal exceptions call into UIE with exception address as first
+ * parameter. This is calculated differently depending on which exception
+ * we're in. Second parameter is exception number, used for a string lookup
+ * in UIE. */
+undef_instr_handler:
+    mov    r0, lr
+    mov    r1, #0
+    b      UIE
+/* We run supervisor mode most of the time, and should never see a software
+ * exception being thrown. Perhaps make it illegal and call UIE? */
+software_int_handler:
+reserved_handler:
+    movs   pc, lr
+prefetch_abort_handler:
+    sub    r0, lr, #4
+    mov    r1, #1
+    b      UIE
+data_abort_handler:
+    sub    r0, lr, #8 
+    mov    r1, #2
+    b      UIE

diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S new file mode 100644 index 0000000000..0dcc203844 --- /dev/null +++ b/firmware/target/arm/s5l8700/crt0.S
@@ -0,0 +1,320 @@
	1	/***************************************************************************
	2	* __________ __ ___.
	3	* Open \______ \ ____ ____ \| \| _\_ \|__ _______ ___
	4	* Source \| _// _ \_/ ___\\| \|/ /\| __ \ / _ \ \/ /
	5	* Jukebox \| \| ( <_> ) \___\| < \| \_\ ( <_> > < <
	6	* Firmware \|____\|_ /\____/ \___ >__\|_ \\|___ /\____/__/\_ \
	7	* \/ \/ \/ \/ \/
	8	* $Id: crt0.S 18776 2008-10-11 18:32:17Z gevaerts $
	9	*
	10	* Copyright (C) 2008 by Marcoen Hirschberg
	11	* Copyright (C) 2008 by Denes Balatoni
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License
	15	* as published by the Free Software Foundation; either version 2
	16	* of the License, or (at your option) any later version.
	17	*
	18	* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
	19	* KIND, either express or implied.
	20	*
	21	****************************************************************************/
	22	#include "config.h"
	23	#include "cpu.h"
	24
	25	.section .intvect,"ax",%progbits
	26	.global _start
	27	.global _newstart
	28	/* Exception vectors */
	29	_start:
	30	b _newstart
	31	ldr pc, =undef_instr_handler
	32	ldr pc, =software_int_handler
	33	ldr pc, =prefetch_abort_handler
	34	ldr pc, =data_abort_handler
	35	ldr pc, =reserved_handler
	36	ldr pc, =irq_handler
	37	ldr pc, =fiq_handler
	38	#if CONFIG_CPU==S5L8700
	39	.word 0x43554644 /* DFUC */
	40	#endif
	41	.ltorg
	42	_newstart:
	43	ldr pc, =newstart2 // we do not want to execute from 0x0 as iram will be mapped there
	44	.section .init.text,"ax",%progbits
	45	newstart2:
	46	msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
	47
	48	mov r1, #0x80
	49	mrc 15, 0, r0, c1, c0, 0
	50	orr r0, r0, r1
	51	mcr 15, 0, r0, c1, c0, 0 // set bigendian
	52
	53	ldr r1, =0x3c800000 // disable watchdog
	54	mov r0, #0xa5
	55	str r0, [r1]
	56
	57	mov r0, #0
	58	ldr r1, =0x39c00008
	59	str r0, [r1] // mask all interrupts
	60	ldr r1, =0x39c00020
	61	str r0, [r1] // mask all external interrupts
	62	mvn r0, #0
	63	mov r1, #0x39c00000
	64	str r0, [r1] // irq priority
	65	ldr r1, =0x39c00010
	66	str r0, [r1] // clear pending interrupts
	67	ldr r1, =0x39c0001c
	68	str r0, [r1] // clear pending external interrupts
	69
	70	// ldr r1, =0x3cf00000
	71	// ldr r0, [r1]
	72	// mvn r2, #0x30
	73	// and r0, r0, r2
	74	// mov r2, #0x10
	75	// orr r0, r0, r2
	76	// str r0, [r1]
	77	// ldr r1, =0x3cf00004
	78	// ldr r0, [r1]
	79	// mov r2, #4
	80	// orr r0, r0, r2
	81	// str r0, [r1] // switch backlight on
	82
	83	ldr r1, =0x3c500000 // CLKCON
	84	ldr r0, =0x00800080
	85	str r0, [r1]
	86	ldr r1, =0x3c500024 // PLLCON
	87	mov r0, #0
	88	str r0, [r1]
	89	ldr r1, =0x3c500004 // PLL0PMS
	90	ldr r0, =0x1ad200
	91	str r0, [r1]
	92	ldr r1, =0x3c500014 // PLL0LCNT
	93	ldr r0, =8100
	94	str r0, [r1]
	95	ldr r1, =0x3c500024 // PLLCON
	96	mov r0, #1
	97	str r0, [r1]
	98	ldr r1, =0x3c500020 // PLLLOCK
	99	1:
	100	ldr r0, [r1]
	101	tst r0, #1
	102	beq 1b
	103	ldr r1, =0x3c50003c // CLKCON2
	104	mov r0, #0x80
	105	str r0, [r1]
	106	ldr r1, =0x3c500000 // CLKCON
	107	ldr r0, =0x20803180
	108	str r0, [r1] // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
	109
	110	ldr r2, =0xc0000078
	111	mrc 15, 0, r0, c1, c0, 0
	112	mvn r1, #0xc0000000
	113	and r0, r0, r1
	114	orr r0, r0, r2
	115	mcr 15, 0, r0, c1, c0, 0 // asynchronous clocking mode
	116	nop
	117	nop
	118	nop
	119	nop
	120
	121	// ldr r0, =0x10100000
	122	// ldr r1, =0x38200034
	123	// str r0, [r1] // SRAM0/1 data width 16 bit
	124	// ldr r0, =0x00220922
	125	// ldr r7, =0x38200038
	126	// str r0, [r7] // SRAM0/1 clocks
	127	// ldr r0, =0x00220922
	128	// ldr r9, =0x3820003c
	129	// str r0, [r9] // SRAM2/3 clocks
	130	// nop
	131	// nop
	132	// nop
	133	// nop
	134
	135	ldr r1, =0x3c500000
	136	mov r0, #0 // 0x0
	137	str r0, [r1, #40] // enable clock for all peripherals
	138	mov r0, #0 // 0x0
	139	str r0, [r1, #44] // do not enter any power saving mode
	140
	141	mov r1, #0x1
	142	mrc 15, 0, r0, c1, c0, 0
	143	bic r0, r0, r1
	144	mcr 15, 0, r0, c1, c0, 0 // disable protection unit
	145
	146	mov r1, #0x4
	147	mrc 15, 0, r0, c1, c0, 0
	148	bic r0, r0, r1
	149	mcr 15, 0, r0, c1, c0, 0 // dcache disable
	150
	151	mov r1, #0x1000
	152	mrc 15, 0, r0, c1, c0, 0
	153	bic r0, r0, r1
	154	mcr 15, 0, r0, c1, c0, 0 // icache disable
	155
	156	mov r1, #0
	157	1:
	158	mov r0, #0
	159	2:
	160	orr r2, r1, r0
	161	mcr 15, 0, r2, c7, c14, 2 // clean and flush dcache single entry
	162	add r0, r0, #0x10
	163	cmp r0, #0x40
	164	bne 2b
	165	add r1, r1, #0x4000000
	166	cmp r1, #0x0
	167	bne 1b
	168	nop
	169	nop
	170	mov r0, #0
	171	mcr 15, 0, r0, c7, c10, 4 // clean and flush whole dcache
	172
	173	mov r0, #0
	174	mcr 15, 0, r0, c7, c5, 0 // flush icache
	175
	176	mov r0, #0
	177	mcr 15, 0, r0, c7, c6, 0 // flush dcache
	178
	179	mov r0, #0x3f
	180	mcr 15, 0, r0, c6, c0, 1
	181	mov r0, #0x2f
	182	mcr 15, 0, r0, c6, c1, 1
	183	ldr r0, =0x0800002f
	184	mcr 15, 0, r0, c6, c2, 1
	185	ldr r0, =0x22000023
	186	mcr 15, 0, r0, c6, c3, 1
	187	ldr r0, =0x24000027
	188	mcr 15, 0, r0, c6, c4, 1
	189	mov r0, #0x3f
	190	mcr 15, 0, r0, c6, c0, 0
	191	mov r0, #0x2f
	192	mcr 15, 0, r0, c6, c1, 0
	193	ldr r0, =0x0800002f
	194	mcr 15, 0, r0, c6, c2, 0
	195	ldr r0, =0x22000023
	196	mcr 15, 0, r0, c6, c3, 0
	197	ldr r0, =0x24000029
	198	mcr 15, 0, r0, c6, c4, 0
	199	mov r0, #0x1e
	200	mcr 15, 0, r0, c2, c0, 1
	201	mov r0, #0x1e
	202	mcr 15, 0, r0, c2, c0, 0
	203	mov r0, #0x1e
	204	mcr 15, 0, r0, c3, c0, 0
	205	ldr r0, =0x0000ffff
	206	mcr 15, 0, r0, c5, c0, 1
	207	ldr r0, =0x0000ffff
	208	mcr 15, 0, r0, c5, c0, 0 // set up protection and caching
	209
	210	mov r1, #0x4
	211	mrc 15, 0, r0, c1, c0, 0
	212	orr r0, r0, r1
	213	mcr 15, 0, r0, c1, c0, 0 // dcache enable
	214
	215	mov r1, #0x1000
	216	mrc 15, 0, r0, c1, c0, 0
	217	orr r0, r0, r1
	218	mcr 15, 0, r0, c1, c0, 0 // icache enable
	219
	220	mov r1, #0x1
	221	mrc 15, 0, r0, c1, c0, 0
	222	orr r0, r0, r1
	223	mcr 15, 0, r0, c1, c0, 0 // enable protection unit
	224
	225
	226	/* Copy interrupt vectors to iram */
	227	ldr r2, =_intvectstart
	228	ldr r3, =_intvectend
	229	ldr r4, =_intvectcopy
	230	1:
	231	cmp r3, r2
	232	ldrhi r1, [r4], #4
	233	strhi r1, [r2], #4
	234	bhi 1b
	235
	236	/* Initialise bss section to zero */
	237	ldr r2, =_edata
	238	ldr r3, =_end
	239	mov r4, #0
	240	1:
	241	cmp r3, r2
	242	strhi r4, [r2], #4
	243	bhi 1b
	244
	245	/* Copy icode and data to ram */
	246	ldr r2, =_datastart
	247	ldr r3, =_dataend
	248	ldr r4, =_datacopy
	249	1:
	250	cmp r3, r2
	251	ldrhi r1, [r4], #4
	252	strhi r1, [r2], #4
	253	bhi 1b
	254
	255	/* Set up some stack and munge it with 0xdeadbeef */
	256	ldr sp, =_stackend
	257	ldr r2, =_stackbegin
	258	ldr r3, =0xdeadbeef
	259	1:
	260	cmp sp, r2
	261	strhi r3, [r2], #4
	262	bhi 1b
	263
	264	/* Set up stack for IRQ mode */
	265	msr cpsr_c, #0xd2
	266	ldr sp, =_irqstackend
	267
	268	/* Set up stack for FIQ mode */
	269	msr cpsr_c, #0xd1
	270	ldr sp, =_fiqstackend
	271
	272	/* Let abort and undefined modes use IRQ stack */
	273	msr cpsr_c, #0xd7
	274	ldr sp, =_irqstackend
	275	msr cpsr_c, #0xdb
	276	ldr sp, =_irqstackend
	277
	278	/* Switch back to supervisor mode */
	279	msr cpsr_c, #0xd3
	280
	281	// if we did not switch remap on, device
	282	// would crash when MENU is pressed,
	283	// as that button is connected to BOOT_MODE pin
	284	ldr r1, =0x38200000
	285	ldr r0, [r1]
	286	mvn r2, #0x10000
	287	and r0, r0, r2
	288	mov r2, #0x1
	289	orr r0, r0, r2
	290	str r0, [r1] // remap iram to address 0x0
	291
	292	bl main
	293
	294	.text
	295	/* .global UIE*/
	296
	297	/* All illegal exceptions call into UIE with exception address as first
	298	* parameter. This is calculated differently depending on which exception
	299	* we're in. Second parameter is exception number, used for a string lookup
	300	* in UIE. */
	301	undef_instr_handler:
	302	mov r0, lr
	303	mov r1, #0
	304	b UIE
	305
	306	/* We run supervisor mode most of the time, and should never see a software
	307	* exception being thrown. Perhaps make it illegal and call UIE? */
	308	software_int_handler:
	309	reserved_handler:
	310	movs pc, lr
	311
	312	prefetch_abort_handler:
	313	sub r0, lr, #4
	314	mov r1, #1
	315	b UIE
	316
	317	data_abort_handler:
	318	sub r0, lr, #8
	319	mov r1, #2
	320	b UIE