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Diffstat (limited to 'firmware/target/arm/s5l8700/crt0.S')
-rw-r--r--firmware/target/arm/s5l8700/crt0.S57
1 files changed, 26 insertions, 31 deletions
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S
index aa2923cb29..35c3d7a8de 100644
--- a/firmware/target/arm/s5l8700/crt0.S
+++ b/firmware/target/arm/s5l8700/crt0.S
@@ -61,17 +61,13 @@ newstart2:
61 str r0, [r1] 61 str r0, [r1]
62 62
63 mov r0, #0 63 mov r0, #0
64 ldr r1, =0x39c00008
65 str r0, [r1] // mask all interrupts
66 ldr r1, =0x39c00020
67 str r0, [r1] // mask all external interrupts
68 mvn r0, #0
69 ldr r1, =0x39c0001c
70 str r0, [r1] // clear pending external interrupts
71 mov r1, #0x39c00000 64 mov r1, #0x39c00000
65 str r0, [r1,#0x08] // mask all interrupts
66 str r0, [r1,#0x20] // mask all external interrupts
67 mvn r0, #0
68 str r0, [r1,#0x1c] // clear pending external interrupts
72 str r0, [r1] // irq priority 69 str r0, [r1] // irq priority
73 ldr r1, =0x39c00010 70 str r0, [r1,#0x10] // clear pending interrupts
74 str r0, [r1] // clear pending interrupts
75 71
76// ldr r1, =0x3cf00000 72// ldr r1, =0x3cf00000
77// ldr r0, [r1] 73// ldr r0, [r1]
@@ -80,11 +76,10 @@ newstart2:
80// mov r2, #0x10 76// mov r2, #0x10
81// orr r0, r0, r2 77// orr r0, r0, r2
82// str r0, [r1] 78// str r0, [r1]
83// ldr r1, =0x3cf00004 79// ldr r0, [r1,#0x04]
84// ldr r0, [r1]
85// mov r2, #4 80// mov r2, #4
86// orr r0, r0, r2 81// orr r0, r0, r2
87// str r0, [r1] // switch backlight on 82// str r0, [r1,#0x04] // switch backlight on
88 83
89#if CONFIG_CPU==S5L8701 84#if CONFIG_CPU==S5L8701
90 ldr r1, =0x38200000 85 ldr r1, =0x38200000
@@ -109,36 +104,29 @@ start_loc:
109#endif /* BOOTLOADER */ 104#endif /* BOOTLOADER */
110#endif /* CONFIG_CPU==S5L8701 */ 105#endif /* CONFIG_CPU==S5L8701 */
111 106
112 ldr r1, =0x3c500000 // CLKCON 107 ldr r1, =0x3c500000
113 ldr r0, =0x00800080 108 ldr r0, =0x00800080
114 str r0, [r1] 109 str r0, [r1] // CLKCON
115 ldr r1, =0x3c500024 // PLLCON
116 mov r0, #0 110 mov r0, #0
117 str r0, [r1] 111 str r0, [r1,#0x24] // PLLCON
118 ldr r1, =0x3c500004 // PLL0PMS
119#ifdef IPOD_NANO2G 112#ifdef IPOD_NANO2G
120 ldr r0, =0x21200 // pdiv=2, mdiv=?? sdiv=0 113 ldr r0, =0x21200 // pdiv=2, mdiv=0x12 sdiv=0
121#else 114#else
122 ldr r0, =0x1ad200 115 ldr r0, =0x1ad200 // pdiv=0x1a, mdiv=0xd2 sdiv=0
123#endif 116#endif
124 str r0, [r1] 117 str r0, [r1,#0x04] // PLL0PMS
125 ldr r1, =0x3c500014 // PLL0LCNT
126 ldr r0, =8100 118 ldr r0, =8100
127 str r0, [r1] 119 str r0, [r1,#0x14] // PLL0LCNT
128 ldr r1, =0x3c500024 // PLLCON
129 mov r0, #1 120 mov r0, #1
130 str r0, [r1] 121 str r0, [r1,#0x24] // PLLCON
131 ldr r1, =0x3c500020 // PLLLOCK
1321: 1221:
133 ldr r0, [r1] 123 ldr r0, [r1,#0x20] // PLLLOCK
134 tst r0, #1 124 tst r0, #1
135 beq 1b 125 beq 1b
136 ldr r1, =0x3c50003c // CLKCON2
137 mov r0, #0x80 126 mov r0, #0x80
138 str r0, [r1] 127 str r0, [r1,#0x3c] // CLKCON2
139 ldr r1, =0x3c500000 // CLKCON 128 ldr r0, =0x20803180 // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
140 ldr r0, =0x20803180 129 str r0, [r1] // CLKCON
141 str r0, [r1] // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
142 130
143 ldr r2, =0xc0000078 131 ldr r2, =0xc0000078
144 mrc 15, 0, r0, c1, c0, 0 132 mrc 15, 0, r0, c1, c0, 0
@@ -168,6 +156,13 @@ start_loc:
168/* The following two sections of code (i.e. Nano2G and Meizus) should 156/* The following two sections of code (i.e. Nano2G and Meizus) should
169 be unified at some point. */ 157 be unified at some point. */
170#ifdef IPOD_NANO2G 158#ifdef IPOD_NANO2G
159
160 ldr r1, =0x3c500000
161 ldr r0, =0xffdff7ff
162 str r0, [r1,#0x28] // PWRCON
163 ldr r0, =0xffffef7e
164 str r0, [r1,#0x40] // PWRCONEXT
165
171 mrc 15, 0, r0, c1, c0, 0 166 mrc 15, 0, r0, c1, c0, 0
172 bic r0, r0, #0x1000 167 bic r0, r0, #0x1000
173 bic r0, r0, #0x5 168 bic r0, r0, #0x5