summaryrefslogtreecommitdiff
path: root/firmware/target/arm/s3c2440/gigabeat-fx
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/target/arm/s3c2440/gigabeat-fx')
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c59
1 files changed, 6 insertions, 53 deletions
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
index 14fbcd5cfe..315fc3bf0f 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
@@ -26,12 +26,6 @@
26#include "sound.h" 26#include "sound.h"
27#include "file.h" 27#include "file.h"
28 28
29/* All exact rates for 16.9344MHz clock */
30#define GIGABEAT_11025HZ (0x19 << 1)
31#define GIGABEAT_22050HZ (0x1b << 1)
32#define GIGABEAT_44100HZ (0x11 << 1)
33#define GIGABEAT_88200HZ (0x1f << 1)
34
35/* PCM interrupt routine lockout */ 29/* PCM interrupt routine lockout */
36static struct 30static struct
37{ 31{
@@ -43,11 +37,6 @@ static struct
43 .state = 0, 37 .state = 0,
44}; 38};
45 39
46/* Last samplerate set by pcm_set_frequency */
47static unsigned long pcm_freq = 0; /* 44.1 is default */
48/* Samplerate control for audio codec */
49static int sr_ctrl = 0;
50
51#define FIFO_COUNT ((IISFCON >> 6) & 0x3F) 40#define FIFO_COUNT ((IISFCON >> 6) & 0x3F)
52 41
53/* Setup for the DMA controller */ 42/* Setup for the DMA controller */
@@ -57,22 +46,6 @@ static int sr_ctrl = 0;
57/* Get more data from the callback and top off the FIFO */ 46/* Get more data from the callback and top off the FIFO */
58void fiq_handler(void) __attribute__((interrupt ("FIQ"))); 47void fiq_handler(void) __attribute__((interrupt ("FIQ")));
59 48
60static void _pcm_apply_settings(void)
61{
62 if (pcm_freq != pcm_curr_sampr)
63 {
64 pcm_curr_sampr = pcm_freq;
65 audiohw_set_frequency(sr_ctrl);
66 }
67}
68
69void pcm_apply_settings(void)
70{
71 int status = disable_fiq_save();
72 _pcm_apply_settings();
73 restore_fiq(status);
74}
75
76/* Mask the DMA interrupt */ 49/* Mask the DMA interrupt */
77void pcm_play_lock(void) 50void pcm_play_lock(void)
78{ 51{
@@ -89,8 +62,6 @@ void pcm_play_unlock(void)
89 62
90void pcm_play_dma_init(void) 63void pcm_play_dma_init(void)
91{ 64{
92 pcm_set_frequency(SAMPR_44);
93
94 /* There seem to be problems when changing the IIS interface configuration 65 /* There seem to be problems when changing the IIS interface configuration
95 * when a clock is not present. 66 * when a clock is not present.
96 */ 67 */
@@ -128,13 +99,18 @@ void pcm_postinit(void)
128 pcm_apply_settings(); 99 pcm_apply_settings();
129} 100}
130 101
102void pcm_dma_apply_settings(void)
103{
104 audiohw_set_frequency(pcm_fsel);
105}
106
131/* Connect the DMA and start filling the FIFO */ 107/* Connect the DMA and start filling the FIFO */
132static void play_start_pcm(void) 108static void play_start_pcm(void)
133{ 109{
134 /* clear pending DMA interrupt */ 110 /* clear pending DMA interrupt */
135 SRCPND = DMA2_MASK; 111 SRCPND = DMA2_MASK;
136 112
137 _pcm_apply_settings(); 113 pcm_apply_settings();
138 114
139 /* Flush any pending writes */ 115 /* Flush any pending writes */
140 clean_dcache_range((void*)DISRC2, (DCON2 & 0xFFFFF) * 2); 116 clean_dcache_range((void*)DISRC2, (DCON2 & 0xFFFFF) * 2);
@@ -272,29 +248,6 @@ void fiq_handler(void)
272 } 248 }
273} 249}
274 250
275void pcm_set_frequency(unsigned int frequency)
276{
277 switch(frequency)
278 {
279 case SAMPR_11:
280 sr_ctrl = GIGABEAT_11025HZ;
281 break;
282 case SAMPR_22:
283 sr_ctrl = GIGABEAT_22050HZ;
284 break;
285 default:
286 frequency = SAMPR_44;
287 case SAMPR_44:
288 sr_ctrl = GIGABEAT_44100HZ;
289 break;
290 case SAMPR_88:
291 sr_ctrl = GIGABEAT_88200HZ;
292 break;
293 }
294
295 pcm_freq = frequency;
296}
297
298size_t pcm_get_bytes_waiting(void) 251size_t pcm_get_bytes_waiting(void)
299{ 252{
300 /* lie a little and only return full pairs */ 253 /* lie a little and only return full pairs */