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-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/kernel-meg-fx.c79
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c558
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/lcd-target.h22
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c243
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/system-target.h44
5 files changed, 22 insertions, 924 deletions
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/kernel-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/kernel-meg-fx.c
deleted file mode 100644
index 6cabc8dc81..0000000000
--- a/firmware/target/arm/s3c2440/gigabeat-fx/kernel-meg-fx.c
+++ /dev/null
@@ -1,79 +0,0 @@
1/***************************************************************************
2* __________ __ ___.
3* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7* \/ \/ \/ \/ \/
8* $Id$
9*
10* Copyright (C) 2007 by Michael Sevakis
11*
12* This program is free software; you can redistribute it and/or
13* modify it under the terms of the GNU General Public License
14* as published by the Free Software Foundation; either version 2
15* of the License, or (at your option) any later version.
16*
17* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18* KIND, either express or implied.
19*
20****************************************************************************/
21#include "config.h"
22#include "system.h"
23#include "kernel.h"
24#include "timer.h"
25#include "thread.h"
26
27void tick_start(unsigned int interval_in_ms)
28{
29 /*
30 * Based on default PCLK of 49.1568MHz - scaling chosen to give
31 * remainder-free result for tick interval of 10ms (100Hz)
32 * Timer input clock frequency =
33 * fPCLK / {prescaler value+1} / {divider value}
34 * TIMER_FREQ = 49156800 / 2
35 * 146300 = TIMER_FREQ / 21 / 8
36 * 49156800 = 19*11*(7)*7*5*5*(3)*2*2*2*2*2*2
37 * 21 = 7*3
38 */
39
40 /* stop timer 4 */
41 TCON &= ~(1 << 20);
42 /* Set the count for timer 4 */
43 TCNTB4 = (TIMER_FREQ / TIMER234_PRESCALE / 8) * interval_in_ms / 1000;
44 /* Set the the prescaler value for timers 2,3, and 4 */
45 TCFG0 = (TCFG0 & ~0xff00) | ((TIMER234_PRESCALE-1) << 8);
46 /* DMA mode off, MUX4 = 1/16 */
47 TCFG1 = (TCFG1 & ~0xff0000) | 0x030000;
48 /* set manual bit */
49 TCON |= 1 << 21;
50 /* reset manual bit */
51 TCON &= ~(1 << 21);
52
53 /* interval mode */
54 TCON |= 1 << 22;
55 /* start timer 4 */
56 TCON |= (1 << 20);
57
58 /* timer 4 unmask interrupts */
59 INTMSK &= ~TIMER4_MASK;
60}
61
62#ifdef BOOTLOADER
63void tick_stop(void)
64{
65 s3c_regset32(&INTMSK, TIMER4_MASK);
66 TCON &= ~(1 << 20);
67 SRCPND = TIMER4_MASK;
68 INTPND = TIMER4_MASK;
69}
70#endif
71
72void TIMER4(void)
73{
74 /* Run through the list of tick tasks */
75 call_tick_tasks();
76
77 SRCPND = TIMER4_MASK;
78 INTPND = TIMER4_MASK;
79}
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c
deleted file mode 100644
index 661ae8e6a9..0000000000
--- a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c
+++ /dev/null
@@ -1,558 +0,0 @@
1/***************************************************************************
2* __________ __ ___.
3* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7* \/ \/ \/ \/ \/
8* $Id$
9*
10* Copyright (C) 2007 by Greg White
11*
12* This program is free software; you can redistribute it and/or
13* modify it under the terms of the GNU General Public License
14* as published by the Free Software Foundation; either version 2
15* of the License, or (at your option) any later version.
16*
17* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18* KIND, either express or implied.
19*
20****************************************************************************/
21#include <sys/types.h>
22
23#include "config.h"
24#include "system.h"
25#include "cpu.h"
26#include "string.h"
27#include "lcd.h"
28#include "kernel.h"
29#include "lcd-target.h"
30
31#define LCDADDR(x, y) (&lcd_framebuffer[(y)][(x)])
32
33static bool lcd_on = true;
34#if defined(HAVE_LCD_ENABLE) || defined(HAVE_LCD_SLEEP)
35static bool lcd_powered = true;
36#endif
37static unsigned lcd_yuv_options = 0;
38/*
39** This is imported from lcd-16bit.c
40*/
41extern struct viewport* current_vp;
42
43/* Copies a rectangle from one framebuffer to another. Can be used in
44 single transfer mode with width = num pixels, and height = 1 which
45 allows a full-width rectangle to be copied more efficiently. */
46extern void lcd_copy_buffer_rect(fb_data *dst, const fb_data *src,
47 int width, int height);
48
49#if defined(HAVE_LCD_ENABLE) || defined(HAVE_LCD_SLEEP)
50bool lcd_active(void)
51{
52 return lcd_on;
53}
54#endif
55
56static unsigned int LCDBANK(unsigned int address)
57{
58 return ((address >> 22) & 0xff);
59}
60
61static unsigned int LCDBASEU(unsigned int address)
62{
63 return (address & ((1 << 22)-1)) >> 1;
64}
65
66static unsigned int LCDBASEL(unsigned int address)
67{
68 address += 320*240*2;
69 return (address & ((1 << 22)-1)) >> 1;
70}
71
72static inline void delay_cycles(volatile int delay)
73{
74 while(delay>0) delay--;
75}
76
77static void LCD_CTRL_setup(void)
78{
79 /* ENVID = 0, BPPMODE = 16 bpp, PNRMODE = TFT, MMODE = Each Frame, CLKVAL = 8 */
80 LCDCON1 = 0x878;
81
82 /* VCPW = 1, VFPD = 5, LINEVAL = 319, VBPD = 7 */
83 LCDCON2 = 0x74FC141;
84
85 /* HFPD = 9, HOZVAL = 239, HBPD = 7 */
86 LCDCON3 = 0x38EF09;
87
88 /* HSPW = 7 */
89 LCDCON4 = 7;
90
91 /* HWSWP = 1, INVVFRAM = 1, INVVLINE = 1, FRM565 = 1, All others = 0 */
92 LCDCON5 = 0xB01;
93
94 LCDSADDR1 = (LCDBANK((unsigned)FRAME) << 21) | (LCDBASEU((unsigned)FRAME));
95 LCDSADDR2 = LCDBASEL((unsigned)FRAME);
96 LCDSADDR3 = 0x000000F0;
97}
98
99static void LCD_CTRL_clock(bool onoff)
100{
101 if(onoff)
102 {
103 GPCCON &= ~0xFFF000FC;
104 GPDCON &= ~0xFFF0FFF0;
105
106 GPCCON |= 0xAAA000A8;
107 GPCUP |= 0xFC0E;
108
109 GPDCON |= 0xAAA0AAA0;
110 GPDUP |= 0xFCFC;
111
112 s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */
113 LCDCON1 |=0x01;
114 }
115 else
116 {
117 GPCCON &= ~0xFFF000FC;
118 GPCUP &= ~0xFC0E;
119
120 GPDCON &= ~0xFFF0FFF0;
121 GPDUP &= ~0xFCFC;
122
123 LCDCON1 &= ~1; /* Must diable first or bus may freeze */
124 s3c_regclr32(&CLKCON, 0x20); /* disable LCD clock */
125 }
126}
127
128static void reset_LCD(bool reset)
129{
130 GPBCON&=~0xC000;
131 GPBCON|=0x4000;
132 if(reset)
133 GPBDAT|=0x80;
134 else
135 GPBDAT&=~0x80;
136}
137
138static void LCD_SPI_send(const unsigned char *array, int count)
139{
140 while (count--)
141 {
142 while ((SPSTA0&0x01)==0){};
143 SPTDAT0=*array++;
144 }
145}
146
147static void LCD_SPI_setreg(unsigned char reg, unsigned char value)
148{
149 unsigned char regval[] =
150 {
151 0x00,reg,0x01,value
152 };
153 LCD_SPI_send(regval, sizeof(regval));
154}
155
156static void LCD_SPI_SS(bool select)
157{
158 delay_cycles(0x4FFF);
159
160 GPBCON&=~0x30000;
161 GPBCON|=0x10000;
162
163 if(select)
164 GPBDAT|=0x100;
165 else
166 GPBDAT&=~0x100;
167}
168
169static void LCD_SPI_start(void)
170{
171 s3c_regset32(&CLKCON, 0x40000); /* enable SPI clock */
172 LCD_SPI_SS(false);
173 SPCON0=0x3E;
174 SPPRE0=24;
175
176 reset_LCD(true);
177 LCD_SPI_SS(true);
178}
179
180static void LCD_SPI_stop(void)
181{
182 LCD_SPI_SS(false);
183
184 SPCON0 &= ~0x10;
185 s3c_regclr32(&CLKCON, 0x40000); /* disable SPI clock */
186}
187
188static void LCD_SPI_init(void)
189{
190 /*
191 * SPI setup - Some of these registers are known; they are documented in
192 * the wiki. Many thanks to Alex Gerchanovsky for discovering this
193 * sequence.
194 */
195
196 LCD_CTRL_clock(true);
197
198 LCD_SPI_start();
199 LCD_SPI_setreg(0x0F, 0x01);
200 LCD_SPI_setreg(0x09, 0x06);
201 LCD_SPI_setreg(0x16, 0xA6);
202 LCD_SPI_setreg(0x1E, 0x49);
203 LCD_SPI_setreg(0x1F, 0x26);
204 LCD_SPI_setreg(0x0B, 0x2F);
205 LCD_SPI_setreg(0x0C, 0x2B);
206 LCD_SPI_setreg(0x19, 0x5E);
207 LCD_SPI_setreg(0x1A, 0x15);
208 LCD_SPI_setreg(0x1B, 0x15);
209 LCD_SPI_setreg(0x1D, 0x01);
210 LCD_SPI_setreg(0x00, 0x03);
211 LCD_SPI_setreg(0x01, 0x10);
212 LCD_SPI_setreg(0x02, 0x0A);
213 LCD_SPI_setreg(0x06, 0x04); /* Set the orientation */
214 LCD_SPI_setreg(0x08, 0x2E);
215 LCD_SPI_setreg(0x24, 0x12);
216 LCD_SPI_setreg(0x25, 0x3F);
217 LCD_SPI_setreg(0x26, 0x0B);
218 LCD_SPI_setreg(0x27, 0x00);
219 LCD_SPI_setreg(0x28, 0x00);
220 LCD_SPI_setreg(0x29, 0xF6);
221 LCD_SPI_setreg(0x2A, 0x03);
222 LCD_SPI_setreg(0x2B, 0x0A);
223 LCD_SPI_setreg(0x04, 0x01); /* Turn the display on */
224 LCD_SPI_stop();
225}
226
227/* LCD init */
228void lcd_init_device(void)
229{
230#ifdef BOOTLOADER
231 int i;
232 /* When the Rockbox bootloader starts the framebuffer address is changed
233 * but the LCD display should stay the same til an lcd_update() occurs.
234 * This copies the data from the old framebuffer to the new one to make the
235 * change non-visable to the user.
236 */
237 unsigned short *buf = (unsigned short*)(FRAME);
238 unsigned short *oldbuf = (unsigned short*)(LCDSADDR1<<1);
239
240 /* The Rockbox bootloader is transitioning from RGB555I to RGB565 mode
241 so convert the frambuffer data accordingly */
242 for(i=0; i< 320*240; i++)
243 {
244 *(buf++) = ((*oldbuf>>1) & 0x1F) | (*oldbuf & 0xffc0);
245 oldbuf++;
246 }
247#endif
248
249 /* Set pins up */
250
251 GPHUP &= 0x600;
252
253 GPECON |= 0x0A800000;
254 GPEUP |= 0x3800;
255
256 GPBUP |= 0x181;
257
258 s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */
259
260 LCD_CTRL_setup();
261 LCD_SPI_init();
262}
263
264#if defined(HAVE_LCD_SLEEP)
265static void LCD_SPI_powerdown(void)
266{
267 lcd_powered = false;
268
269 LCD_SPI_start();
270 LCD_SPI_setreg(0x04, 0x00);
271 LCD_SPI_stop();
272
273 reset_LCD(false); /* This makes a big difference on power */
274 LCD_CTRL_clock(false);
275}
276
277void lcd_sleep(void)
278{
279 if (lcd_powered)
280 {
281 /* "not powered" implies "disabled" */
282 if (lcd_on)
283 lcd_enable(false);
284
285 LCD_SPI_powerdown();
286 }
287}
288#endif
289
290#if defined(HAVE_LCD_ENABLE)
291static void LCD_SPI_powerup(void)
292{
293 LCD_CTRL_clock(true);
294
295 LCD_SPI_start();
296 LCD_SPI_setreg(0x04, 0x01);
297 LCD_SPI_stop();
298
299 lcd_powered = true;
300}
301
302void lcd_enable(bool state)
303{
304 if (state == lcd_on)
305 return;
306
307 if(state)
308 {
309 /* "enabled" implies "powered" */
310 if (!lcd_powered)
311 {
312 LCD_SPI_powerup();
313 /* Wait long enough for a frame to be written - yes, it
314 * takes awhile. */
315 sleep(HZ/5);
316 }
317
318 lcd_on = true;
319 lcd_update();
320 lcd_activation_call_hook();
321 }
322 else
323 {
324 lcd_on = false;
325 }
326}
327#endif
328
329void lcd_set_flip(bool yesno) {
330 if (!lcd_on)
331 return;
332
333 LCD_SPI_start();
334 if(yesno)
335 {
336 LCD_SPI_setreg(0x06, 0x02);
337 }
338 else
339 {
340 LCD_SPI_setreg(0x06, 0x04);
341 }
342 LCD_SPI_stop();
343}
344
345int lcd_default_contrast(void)
346{
347 return DEFAULT_CONTRAST_SETTING;
348}
349
350void lcd_set_contrast(int val) {
351 if (!lcd_on)
352 return;
353
354 LCD_SPI_start();
355 LCD_SPI_setreg(0x0B, (unsigned char) val);
356 LCD_SPI_stop();
357}
358
359void lcd_set_invert_display(bool yesno) {
360 if (!lcd_on)
361 return;
362
363 LCD_SPI_start();
364 if(yesno)
365 {
366 LCD_SPI_setreg(0x27, 0x10);
367 }
368 else
369 {
370 LCD_SPI_setreg(0x27, 0x00);
371 }
372 LCD_SPI_stop();
373}
374
375/* Update a fraction of the display. */
376void lcd_update_rect(int x, int y, int width, int height)
377{
378 fb_data *dst, *src;
379
380 if (!lcd_on)
381 return;
382
383 if (x + width > LCD_WIDTH)
384 width = LCD_WIDTH - x; /* Clip right */
385 if (x < 0)
386 width += x, x = 0; /* Clip left */
387 if (width <= 0)
388 return; /* nothing left to do */
389
390 if (y + height > LCD_HEIGHT)
391 height = LCD_HEIGHT - y; /* Clip bottom */
392 if (y < 0)
393 height += y, y = 0; /* Clip top */
394 if (height <= 0)
395 return; /* nothing left to do */
396
397 /* TODO: It may be faster to swap the addresses of lcd_driver_framebuffer
398 * and lcd_framebuffer */
399 dst = (fb_data *)FRAME + LCD_WIDTH*y + x;
400 src = &lcd_framebuffer[y][x];
401
402 /* Copy part of the Rockbox framebuffer to the second framebuffer */
403 if (width < LCD_WIDTH)
404 {
405 /* Not full width - do line-by-line */
406 lcd_copy_buffer_rect(dst, src, width, height);
407 }
408 else
409 {
410 /* Full width - copy as one line */
411 lcd_copy_buffer_rect(dst, src, LCD_WIDTH*height, 1);
412 }
413}
414
415/* Update the display.
416 This must be called after all other LCD functions that change the display. */
417void lcd_update(void)
418{
419 if (!lcd_on)
420 return;
421
422 lcd_copy_buffer_rect((fb_data *)FRAME, &lcd_framebuffer[0][0],
423 LCD_WIDTH*LCD_HEIGHT, 1);
424}
425
426void lcd_bitmap_transparent_part(const fb_data *src, int src_x, int src_y,
427 int stride, int x, int y, int width,
428 int height)
429{
430 int w, px;
431 fb_data *dst;
432
433 if (x + width > current_vp->width)
434 width = current_vp->width - x; /* Clip right */
435
436 if (x < 0) /* Clip left */
437 {
438 width += x;
439 src_x -= x;
440 x = 0;
441 }
442
443 if (width <= 0)
444 return; /* nothing left to do */
445
446 if (y + height > current_vp->height)
447 height = current_vp->height - y; /* Clip bottom */
448
449 if (y < 0) /* Clip top */
450 {
451 height += y;
452 src_y -= y;
453 y = 0;
454 }
455
456 if (height <= 0)
457 return; /* nothing left to do */
458
459 src += stride * src_y + src_x; /* move starting point */
460 dst = &lcd_framebuffer[current_vp->y+y][current_vp->x+x];
461
462 asm volatile (
463 ".rowstart: \r\n"
464 "mov %[w], %[width] \r\n" /* Load width for inner loop */
465 ".nextpixel: \r\n"
466 "ldrh %[px], [%[s]], #2 \r\n" /* Load src pixel */
467 "add %[d], %[d], #2 \r\n" /* Uncoditionally increment dst */
468 "cmp %[px], %[fgcolor] \r\n" /* Compare to foreground color */
469 "streqh %[fgpat], [%[d], #-2] \r\n" /* Store foregroud if match */
470 "cmpne %[px], %[transcolor] \r\n" /* Compare to transparent color */
471 "strneh %[px], [%[d], #-2] \r\n" /* Store dst if not transparent */
472 "subs %[w], %[w], #1 \r\n" /* Width counter has run down? */
473 "bgt .nextpixel \r\n" /* More in this row? */
474 "add %[s], %[s], %[sstp], lsl #1 \r\n" /* Skip over to start of next line */
475 "add %[d], %[d], %[dstp], lsl #1 \r\n"
476 "subs %[h], %[h], #1 \r\n" /* Height counter has run down? */
477 "bgt .rowstart \r\n" /* More rows? */
478 : [w]"=&r"(w), [h]"+&r"(height), [px]"=&r"(px),
479 [s]"+&r"(src), [d]"+&r"(dst)
480 : [width]"r"(width),
481 [sstp]"r"(stride - width),
482 [dstp]"r"(LCD_WIDTH - width),
483 [transcolor]"r"(TRANSPARENT_COLOR),
484 [fgcolor]"r"(REPLACEWITHFG_COLOR),
485 [fgpat]"r"(current_vp->fg_pattern)
486 );
487}
488
489void lcd_yuv_set_options(unsigned options)
490{
491 lcd_yuv_options = options;
492}
493
494/* Line write helper function for lcd_yuv_blit. Write two lines of yuv420. */
495extern void lcd_write_yuv420_lines(fb_data *dst,
496 unsigned char const * const src[3],
497 int width,
498 int stride);
499extern void lcd_write_yuv420_lines_odither(fb_data *dst,
500 unsigned char const * const src[3],
501 int width,
502 int stride,
503 int x_screen, /* To align dither pattern */
504 int y_screen);
505/* Performance function to blit a YUV bitmap directly to the LCD */
506/* For the Gigabeat - show it rotated */
507/* So the LCD_WIDTH is now the height */
508void lcd_blit_yuv(unsigned char * const src[3],
509 int src_x, int src_y, int stride,
510 int x, int y, int width, int height)
511{
512 /* Caches for chroma data so it only need be recaculated every other
513 line */
514 unsigned char const * yuv_src[3];
515 off_t z;
516
517 if (!lcd_on)
518 return;
519
520 /* Sorry, but width and height must be >= 2 or else */
521 width &= ~1;
522 height >>= 1;
523
524 y = LCD_WIDTH - 1 - y;
525 fb_data *dst = (fb_data*)FRAME + x * LCD_WIDTH + y;
526
527 z = stride*src_y;
528 yuv_src[0] = src[0] + z + src_x;
529 yuv_src[1] = src[1] + (z >> 2) + (src_x >> 1);
530 yuv_src[2] = src[2] + (yuv_src[1] - src[1]);
531
532 if (lcd_yuv_options & LCD_YUV_DITHER)
533 {
534 do
535 {
536 lcd_write_yuv420_lines_odither(dst, yuv_src, width, stride, y, x);
537 yuv_src[0] += stride << 1; /* Skip down two luma lines */
538 yuv_src[1] += stride >> 1; /* Skip down one chroma line */
539 yuv_src[2] += stride >> 1;
540 dst -= 2;
541 y -= 2;
542 }
543 while (--height > 0);
544 }
545 else
546 {
547 do
548 {
549 lcd_write_yuv420_lines(dst, yuv_src, width, stride);
550 yuv_src[0] += stride << 1; /* Skip down two luma lines */
551 yuv_src[1] += stride >> 1; /* Skip down one chroma line */
552 yuv_src[2] += stride >> 1;
553 dst -= 2;
554 }
555 while (--height > 0);
556 }
557}
558
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-target.h
index cb82a8076f..c136a2052d 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-target.h
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-target.h
@@ -21,3 +21,25 @@
21 21
22extern void lcd_enable(bool state); 22extern void lcd_enable(bool state);
23 23
24/* Config values for LCDCON1 */
25/* ENVID = 0, BPPMODE = 16 bpp, PNRMODE = TFT, MMODE = Each Frame, CLKVAL = 8 */
26#define LCD_CLKVAL 8
27#define LCD_MMODE 0
28#define LCD_PNRMODE 3
29#define LCD_BPPMODE 12
30#define LCD_ENVID 1
31
32/* Config values for LCDCON2 */
33/* VCPW = 1, VFPD = 5, VBPD = 7 */
34#define LCD_UPPER_MARGIN 7
35#define LCD_LOWER_MARGIN 5
36#define LCD_VSYNC_LEN 1
37
38/* Config values for LCDCON3 */
39/* HFPD = 9, HBPD = 7 */
40#define LCD_LEFT_MARGIN 7
41#define LCD_RIGHT_MARGIN 9
42
43/* Config values for LCDCON4 */
44/* HSPW = 7 */
45#define LCD_HSYNC_LEN 7
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c
deleted file mode 100644
index 79d592091e..0000000000
--- a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c
+++ /dev/null
@@ -1,243 +0,0 @@
1/***************************************************************************
2* __________ __ ___.
3* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7* \/ \/ \/ \/ \/
8* $Id$
9*
10* Copyright (C) 2007 by Michael Sevakis
11*
12* This program is free software; you can redistribute it and/or
13* modify it under the terms of the GNU General Public License
14* as published by the Free Software Foundation; either version 2
15* of the License, or (at your option) any later version.
16*
17* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18* KIND, either express or implied.
19*
20****************************************************************************/
21#include "kernel.h"
22#include "system.h"
23#include "panic.h"
24#include "mmu-arm.h"
25#include "cpu.h"
26
27#define default_interrupt(name) \
28 extern __attribute__((weak,alias("UIRQ"))) void name (void)
29
30default_interrupt(EINT0);
31default_interrupt(EINT1);
32default_interrupt(EINT2);
33default_interrupt(EINT3);
34default_interrupt(EINT4_7);
35default_interrupt(EINT8_23);
36default_interrupt(CAM);
37default_interrupt(nBATT_FLT);
38default_interrupt(TICK);
39default_interrupt(WDT_AC97);
40default_interrupt(TIMER0);
41default_interrupt(TIMER1);
42default_interrupt(TIMER2);
43default_interrupt(TIMER3);
44default_interrupt(TIMER4);
45default_interrupt(UART2);
46default_interrupt(LCD);
47default_interrupt(DMA0);
48default_interrupt(DMA1);
49default_interrupt(DMA2);
50default_interrupt(DMA3);
51default_interrupt(SDI);
52default_interrupt(SPI0);
53default_interrupt(UART1);
54default_interrupt(NFCON);
55default_interrupt(USBD);
56default_interrupt(USBH);
57default_interrupt(IIC);
58default_interrupt(UART0);
59default_interrupt(SPI1);
60default_interrupt(RTC);
61default_interrupt(ADC);
62
63static void (* const irqvector[32])(void) __attribute__((__used__)) =
64{
65 EINT0, EINT1, EINT2, EINT3,
66 EINT4_7, EINT8_23, CAM, nBATT_FLT, TICK, WDT_AC97,
67 TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, UART2,
68 LCD, DMA0, DMA1, DMA2, DMA3, SDI,
69 SPI0, UART1, NFCON, USBD, USBH, IIC,
70 UART0, SPI1, RTC, ADC,
71};
72
73static const char * const irqname[32] =
74{
75 "EINT0", "EINT1", "EINT2", "EINT3",
76 "EINT4_7", "EINT8_23", "CAM", "nBATT_FLT", "TICK", "WDT_AC97",
77 "TIMER0", "TIMER1", "TIMER2", "TIMER3", "TIMER4", "UART2",
78 "LCD", "DMA0", "DMA1", "DMA2", "DMA3", "SDI",
79 "SPI0", "UART1", "NFCON", "USBD", "USBH", "IIC",
80 "UART0", "SPI1", "RTC", "ADC"
81};
82
83static void UIRQ(void)
84{
85 unsigned int offset = INTOFFSET;
86 panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
87}
88
89void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
90void irq_handler(void)
91{
92 asm volatile (
93 "sub lr, lr, #4 \r\n"
94 "stmfd sp!, {r0-r3, ip, lr} \r\n"
95 "mov r0, #0x4a000000 \r\n" /* INTOFFSET = 0x4a000014 */
96 "ldr r0, [r0, #0x14] \r\n"
97 "ldr r1, =irqvector \r\n"
98 "ldr r1, [r1, r0, lsl #2] \r\n"
99 "mov lr, pc \r\n"
100 "bx r1 \r\n"
101 "ldmfd sp!, {r0-r3, ip, pc}^ \r\n"
102 );
103}
104
105void system_reboot(void)
106{
107 WTCON = 0;
108 WTCNT = WTDAT = 1 ;
109 WTCON = 0x21;
110 for(;;)
111 ;
112}
113
114void system_exception_wait(void)
115{
116 INTMSK = 0xFFFFFFFF;
117 while ((GPGDAT & (1 << 0)) == 0); /* Wait for power button */
118}
119
120static void set_page_tables(void)
121{
122 /* map every memory region to itself */
123 map_section(0, 0, 0x1000, CACHE_NONE);
124
125 /* map RAM to 0 and enable caching for it */
126 map_section(0x30000000, 0, 32, CACHE_ALL);
127
128 /* enable buffered writing for the framebuffer */
129 map_section((int)FRAME, (int)FRAME, 1, BUFFERED);
130}
131
132void memory_init(void)
133{
134 ttb_init();
135 set_page_tables();
136 enable_mmu();
137}
138
139void s3c_regmod32(volatile unsigned long *reg, unsigned long bits,
140 unsigned long mask)
141{
142 int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
143 *reg = (*reg & ~mask) | (bits & mask);
144 restore_interrupt(oldstatus);
145}
146
147void s3c_regset32(volatile unsigned long *reg, unsigned long bits)
148{
149 s3c_regmod32(reg, bits, bits);
150}
151
152void s3c_regclr32(volatile unsigned long *reg, unsigned long bits)
153{
154 s3c_regmod32(reg, 0, bits);
155}
156
157#ifdef BOOTLOADER
158void system_prepare_fw_start(void)
159{
160 tick_stop();
161 disable_interrupt(IRQ_FIQ_STATUS);
162 INTMSK = 0xFFFFFFFF;
163}
164#endif
165
166void system_init(void)
167{
168 INTMSK = 0xFFFFFFFF;
169 INTMOD = 0;
170 SRCPND = 0xFFFFFFFF;
171 INTPND = 0xFFFFFFFF;
172 INTSUBMSK = 0xFFFFFFFF;
173 SUBSRCPND = 0xFFFFFFFF;
174
175 GPBCON |= 0x85;
176 GPBDAT |= 0x07;
177 GPBUP |= 0x20F;
178
179 /* Take care of flash related pins */
180 GPCCON |= 0x1000;
181 GPCDAT &= ~0x40;
182 GPCUP |= 0x51;
183
184 GPDCON |= 0x05;
185 GPDUP |= 0x03;
186 GPDDAT &= ~0x03;
187
188 GPFCON |= 0x00000AAA;
189 GPFUP |= 0xFF;
190
191 GPGCON |= 0x01001000;
192 GPGUP |= 0x70;
193
194 GPHCON |= 0x4005;
195 GPHDAT |= 0x03;
196
197 /* TODO: do something with PRIORITY */
198
199 /* Turn off currently-not or never-needed devices.
200 * Be careful here, it is possible to freeze the device by disabling
201 * clocks at the wrong time.
202 *
203 * Turn off AC97, Camera, SPI, IIS, I2C, UARTS, MMC/SD/SDIO Controller
204 * USB device, USB host, NAND flash controller.
205 *
206 * IDLE, Sleep, LCDC, PWM timer, GPIO, RTC, and ADC are untouched (on)
207 */
208 CLKCON &= ~0xFF1ED0;
209
210 CLKSLOW |= 0x80;
211}
212
213int system_memory_guard(int newmode)
214{
215 (void)newmode;
216 return 0;
217}
218
219#ifdef HAVE_ADJUSTABLE_CPU_FREQ
220
221void set_cpu_frequency(long frequency)
222{
223 if (frequency == CPUFREQ_MAX)
224 {
225 asm volatile("mov r0, #0\n"
226 "mrc p15, 0, r0, c1, c0, 0\n"
227 "orr r0, r0, #3<<30\n" /* set to Asynchronous mode*/
228 "mcr p15, 0, r0, c1, c0, 0" : : : "r0");
229
230 FREQ = CPUFREQ_MAX;
231 }
232 else
233 {
234 asm volatile("mov r0, #0\n"
235 "mrc p15, 0, r0, c1, c0, 0\n"
236 "bic r0, r0, #3<<30\n" /* set to FastBus mode*/
237 "mcr p15, 0, r0, c1, c0, 0" : : : "r0");
238
239 FREQ = CPUFREQ_NORMAL;
240 }
241}
242
243#endif
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
deleted file mode 100644
index f310b9ac26..0000000000
--- a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2007 by Greg White
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#ifndef SYSTEM_TARGET_H
22#define SYSTEM_TARGET_H
23
24#include "system-arm.h"
25#include "mmu-arm.h"
26
27#define CPUFREQ_DEFAULT 98784000
28#define CPUFREQ_NORMAL 98784000
29#define CPUFREQ_MAX 296352000
30
31void system_prepare_fw_start(void);
32void tick_stop(void);
33
34/* Functions to set and clear regiser bits atomically */
35
36/* Set and clear register bits */
37void s3c_regmod32(volatile unsigned long *reg, unsigned long bits,
38 unsigned long mask);
39/* Set register bits */
40void s3c_regset32(volatile unsigned long *reg, unsigned long bits);
41/* Clear register bits */
42void s3c_regclr32(volatile unsigned long *reg, unsigned long bits);
43
44#endif /* SYSTEM_TARGET_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-05 23:03:50 +0000