diff options
Diffstat (limited to 'firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c')
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c | 36 |
1 files changed, 1 insertions, 35 deletions
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c index 3bb2801b02..17b0a6966e 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c | |||
@@ -14,7 +14,6 @@ | |||
14 | 14 | ||
15 | #define LCDADDR(x, y) (&lcd_framebuffer[(y)][(x)]) | 15 | #define LCDADDR(x, y) (&lcd_framebuffer[(y)][(x)]) |
16 | 16 | ||
17 | volatile bool use_dma_blit = false; | ||
18 | static volatile bool lcd_on = true; | 17 | static volatile bool lcd_on = true; |
19 | volatile bool lcd_poweroff = false; | 18 | volatile bool lcd_poweroff = false; |
20 | /* | 19 | /* |
@@ -89,40 +88,7 @@ void lcd_update_rect(int x, int y, int width, int height) | |||
89 | sleep(200); | 88 | sleep(200); |
90 | return; | 89 | return; |
91 | } | 90 | } |
92 | if (use_dma_blit) | 91 | memcpy(((char*)FRAME) + (y * sizeof(fb_data) * LCD_WIDTH), ((char *)&lcd_framebuffer) + (y * sizeof(fb_data) * LCD_WIDTH), ((height * sizeof(fb_data) * LCD_WIDTH))); |
93 | { | ||
94 | /* Wait for this controller to stop pending transfer */ | ||
95 | while((DSTAT1 & 0x000fffff)) | ||
96 | CLKCON |= (1 << 2); /* set IDLE bit */ | ||
97 | |||
98 | /* Flush DCache */ | ||
99 | invalidate_dcache_range((void *)(((int) &lcd_framebuffer[0][0])+(y * sizeof(fb_data) * LCD_WIDTH)), (height * sizeof(fb_data) * LCD_WIDTH)); | ||
100 | |||
101 | /* set DMA dest */ | ||
102 | DIDST1 = ((int) FRAME) + (y * sizeof(fb_data) * LCD_WIDTH); | ||
103 | |||
104 | /* FRAME on AHB buf, increment */ | ||
105 | DIDSTC1 = 0; | ||
106 | /* Handshake on AHB, Burst transfer, Whole service, Don't reload, transfer 32-bits */ | ||
107 | DCON1 = ((1<<30) | (1<<28) | (1<<27) | (1<<22) | (2<<20)) | ((height * sizeof(fb_data) * LCD_WIDTH) >> 4); | ||
108 | |||
109 | /* set DMA source */ | ||
110 | DISRC1 = ((int) &lcd_framebuffer[0][0]) + (y * sizeof(fb_data) * LCD_WIDTH) + 0x30000000; | ||
111 | /* memory is on AHB bus, increment addresses */ | ||
112 | DISRCC1 = 0x00; | ||
113 | |||
114 | /* Activate the channel */ | ||
115 | DMASKTRIG1 = 0x2; | ||
116 | |||
117 | /* Start DMA */ | ||
118 | DMASKTRIG1 |= 0x1; | ||
119 | |||
120 | /* Wait for transfer to complete */ | ||
121 | while((DSTAT1 & 0x000fffff)) | ||
122 | CLKCON |= (1 << 2); /* set IDLE bit */ | ||
123 | } | ||
124 | else | ||
125 | memcpy(((char*)FRAME) + (y * sizeof(fb_data) * LCD_WIDTH), ((char *)&lcd_framebuffer) + (y * sizeof(fb_data) * LCD_WIDTH), ((height * sizeof(fb_data) * LCD_WIDTH))); | ||
126 | } | 92 | } |
127 | 93 | ||
128 | 94 | ||