diff options
Diffstat (limited to 'firmware/target/arm/s3c2440/crt0.S')
-rw-r--r-- | firmware/target/arm/s3c2440/crt0.S | 466 |
1 files changed, 312 insertions, 154 deletions
diff --git a/firmware/target/arm/s3c2440/crt0.S b/firmware/target/arm/s3c2440/crt0.S index 4f220f6c7f..7f1ebf8dec 100644 --- a/firmware/target/arm/s3c2440/crt0.S +++ b/firmware/target/arm/s3c2440/crt0.S | |||
@@ -7,7 +7,11 @@ | |||
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id$ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | 10 | * Copyright (C) 2008 by Karl Kurbjun |
11 | * | ||
12 | * Arm bootloader and startup code based on startup.s from the iPodLinux loader | ||
13 | * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org) | ||
14 | * Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org> | ||
11 | * | 15 | * |
12 | * All files in this archive are subject to the GNU General Public License. | 16 | * All files in this archive are subject to the GNU General Public License. |
13 | * See the file COPYING in the source tree root for full license agreement. | 17 | * See the file COPYING in the source tree root for full license agreement. |
@@ -19,73 +23,183 @@ | |||
19 | #include "config.h" | 23 | #include "config.h" |
20 | #include "cpu.h" | 24 | #include "cpu.h" |
21 | 25 | ||
22 | .section .init.text,"ax",%progbits | 26 | /* Exception Handlers */ |
27 | .section .vectors,"ax",%progbits | ||
28 | .code 32 | ||
23 | 29 | ||
24 | .global start | 30 | .global vectors |
25 | start: | 31 | vectors: |
32 | b start | ||
33 | b undef_instr_handler | ||
34 | b software_int_handler | ||
35 | b prefetch_abort_handler | ||
36 | b data_abort_handler | ||
37 | b reserved_handler | ||
38 | b irq_handler | ||
39 | b fiq_handler | ||
40 | |||
41 | /* | ||
42 | * Function: code_copy | ||
43 | * Variables: | ||
44 | * r0 = from | ||
45 | * r1 = to | ||
46 | * r2 = length | ||
47 | */ | ||
26 | 48 | ||
27 | /* Arm bootloader and startup code based on startup.s from the iPodLinux loader | 49 | .section .init.text, "ax", %progbits |
28 | * | 50 | .align 0x04 |
29 | * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org) | 51 | .global word_copy |
30 | * Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org> | 52 | .type word_copy, %function |
31 | * | 53 | word_copy: |
54 | sub r2, r2, #0x04 | ||
55 | cmp r2, #0 | ||
56 | ldrge r3, [r0], #4 | ||
57 | strge r3, [r1], #4 | ||
58 | bgt word_copy | ||
59 | bx lr | ||
60 | .ltorg | ||
61 | .size word_copy, .-word_copy | ||
62 | |||
63 | /* | ||
64 | * Entry: start | ||
65 | * Variables: | ||
66 | * none | ||
32 | */ | 67 | */ |
33 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */ | ||
34 | |||
35 | #if !defined(BOOTLOADER) | ||
36 | /* Copy exception handler code to address 0 */ | ||
37 | ldr r2, =_vectorsstart | ||
38 | ldr r3, =_vectorsend | ||
39 | ldr r4, =_vectorscopy | ||
40 | 1: | ||
41 | cmp r3, r2 | ||
42 | ldrhi r5, [r4], #4 | ||
43 | strhi r5, [r2], #4 | ||
44 | bhi 1b | ||
45 | #endif | ||
46 | 68 | ||
47 | #if !defined(BOOTLOADER) && !defined(STUB) | 69 | .section .init.text,"ax",%progbits |
48 | /* Zero out IBSS */ | 70 | .code 32 |
49 | ldr r2, =_iedata | 71 | .align 0x04 /* Align */ |
50 | ldr r3, =_iend | 72 | .global start |
51 | mov r4, #0 | 73 | start: |
52 | 1: | 74 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */ |
53 | cmp r3, r2 | ||
54 | strhi r4, [r2], #4 | ||
55 | bhi 1b | ||
56 | 75 | ||
57 | /* Copy the IRAM */ | 76 | /* Disable the watchdog */ |
58 | ldr r2, =_iramcopy | 77 | ldr r2, =0x00000000 |
59 | ldr r3, =_iramstart | 78 | mov r1, #0x53000000 |
60 | ldr r4, =_iramend | 79 | str r2, [r1] |
61 | 1: | ||
62 | cmp r4, r3 | ||
63 | ldrhi r5, [r2], #4 | ||
64 | strhi r5, [r3], #4 | ||
65 | bhi 1b | ||
66 | #endif /* !BOOTLOADER, !STUB */ | ||
67 | 80 | ||
68 | /* Initialise bss section to zero */ | 81 | /* Mask all Interupts to be safe */ |
69 | ldr r2, =_edata | 82 | ldr r2, =0xFFFFFFFF |
70 | ldr r3, =_end | 83 | mov r1, #0x4A000000 |
71 | mov r4, #0 | 84 | str r2, [r1] |
72 | 1: | 85 | |
73 | cmp r3, r2 | 86 | /* Submask too */ |
74 | strhi r4, [r2], #4 | 87 | ldr r2, =0x00003FFF |
75 | bhi 1b | 88 | str r2, [r1, #0x1C] |
76 | 89 | ||
77 | /* Set up some stack and munge it with 0xdeadbeef */ | 90 | /* Check if loaded by the old bootloader or by the OF |
78 | ldr sp, =stackend | 91 | * Be careful with code size above this as well. |
79 | mov r3, sp | 92 | */ |
80 | ldr r2, =stackbegin | 93 | |
81 | ldr r4, =0xdeadbeef | 94 | /* Get the execute address (cannot be past 0x100 for this to work */ |
82 | 1: | 95 | ldr r0, =0xffffff00 |
83 | cmp r3, r2 | 96 | and r0, pc, r0 |
84 | strhi r4, [r2], #4 | 97 | |
85 | bhi 1b | 98 | /* Calculate the length of the code needed to run/copy */ |
99 | ldr r1, = _vectorstart | ||
100 | ldr r2, = _iramend | ||
101 | sub r2, r2, r1 | ||
102 | |||
103 | add r3, r2, #0x30000000 | ||
104 | |||
105 | /* Is there enough space to copy without overwriting? */ | ||
106 | cmp r0, r3 | ||
107 | |||
108 | /* There's enough space, skip copying */ | ||
109 | bgt skipreset | ||
110 | |||
111 | /* Is this code running from 0x0? If so skip copy. */ | ||
112 | cmplt r0, #0 | ||
113 | beq skipreset | ||
86 | 114 | ||
87 | #ifdef BOOTLOADER | 115 | /* There's not enough space to copy without overwriting, copy to safe spot |
88 | /* Proper initialization pulled from 0x5070 */ | 116 | * and reset |
117 | */ | ||
118 | mov r1, #0x31000000 /* copy location */ | ||
119 | bl word_copy | ||
120 | |||
121 | mov pc, #0x31000000 | ||
122 | |||
123 | skipreset: | ||
124 | |||
125 | /* Initial Clock Setup */ | ||
126 | mov r2, #0x7 | ||
127 | mov r1, #0x4C000000 | ||
128 | str r2, [r1, #0x14] | ||
129 | |||
130 | mov r2, #0x0 | ||
131 | str r2, [r1, #0x18] | ||
132 | |||
133 | ldr r2, =0xFFFFFFFF | ||
134 | str r2, [r1] | ||
135 | |||
136 | ldr r2, =0x0003C042 | ||
137 | str r2, [r1, #0x08] | ||
138 | |||
139 | nop | ||
140 | nop | ||
141 | nop | ||
142 | nop | ||
143 | nop | ||
144 | nop | ||
145 | nop | ||
146 | nop | ||
147 | |||
148 | ldr r2, =0x000C9042 | ||
149 | str r2, [r1, #0x04] | ||
150 | |||
151 | nop | ||
152 | nop | ||
153 | nop | ||
154 | nop | ||
155 | nop | ||
156 | nop | ||
157 | nop | ||
158 | nop | ||
159 | |||
160 | /* If we want to disable extraneous clocks, uncomment, but it can | ||
161 | * freeze the device | ||
162 | */ | ||
163 | #if 0 | ||
164 | ldr r2, =0x6030 | ||
165 | mov r1, #0x4C000000 | ||
166 | str r2, [r1, #0x0C] | ||
167 | #endif | ||
168 | |||
169 | /* set Bus to Asynchronous mode (full speed) */ | ||
170 | mov r0, #0 | ||
171 | mrc p15, 0, r0, c1, c0, 0 | ||
172 | ldr r1, =0xC0000000 | ||
173 | orr r0, r0, r1 | ||
174 | mcr p15, 0, r0, c1, c0, 0 | ||
175 | |||
176 | /* Setup MISCCR */ | ||
177 | ldr r2, =0x00613020 | ||
178 | mov r1, #0x56000000 | ||
179 | str r2, [r1, #0x80] | ||
180 | |||
181 | /* Setup some unknown outputs in GPB and GPH */ | ||
182 | ldr r2, [r1, #0x10] | ||
183 | mov r3, #0x05 | ||
184 | orr r2, r3, r2 | ||
185 | str r2, [r1, #0x10] | ||
186 | |||
187 | ldr r2, [r1, #0x14] | ||
188 | mov r3, #0x03 | ||
189 | orr r2, r3, r2 | ||
190 | str r2, [r1, #0x14] | ||
191 | |||
192 | ldr r2, [r1, #0x70] | ||
193 | mov r3, #0x05 | ||
194 | orr r2, r3, r2 | ||
195 | str r2, [r1, #0x70] | ||
196 | |||
197 | ldr r2, [r1, #0x74] | ||
198 | mov r3, #0x03 | ||
199 | orr r2, r3, r2 | ||
200 | str r2, [r1, #0x74] | ||
201 | |||
202 | /* Memory setup (taken from 0x5070) */ | ||
89 | 203 | ||
90 | /* BWSCON | 204 | /* BWSCON |
91 | * Reserved 0 | 205 | * Reserved 0 |
@@ -120,7 +234,7 @@ start: | |||
120 | * Disable wait 0 | 234 | * Disable wait 0 |
121 | * Not using UB/LB 0 | 235 | * Not using UB/LB 0 |
122 | */ | 236 | */ |
123 | ldr r2,=0x01055102 | 237 | ldr r2, =0x01055102 |
124 | mov r1, #0x48000000 | 238 | mov r1, #0x48000000 |
125 | str r2, [r1] | 239 | str r2, [r1] |
126 | 240 | ||
@@ -133,8 +247,8 @@ start: | |||
133 | * Chip select setup time: 1 clock 01 | 247 | * Chip select setup time: 1 clock 01 |
134 | * Address setup time: 0 clock 00 | 248 | * Address setup time: 0 clock 00 |
135 | */ | 249 | */ |
136 | ldr r2,=0x00000D60 | 250 | ldr r2, =0x00000D60 |
137 | str r2, [r1, #4] | 251 | str r2, [r1, #0x04] |
138 | 252 | ||
139 | 253 | ||
140 | /* BANKCON1 | 254 | /* BANKCON1 |
@@ -146,8 +260,8 @@ start: | |||
146 | * Chip select setup time: 0 clocks 00 | 260 | * Chip select setup time: 0 clocks 00 |
147 | * Address setup time: 0 clocks 00 | 261 | * Address setup time: 0 clocks 00 |
148 | */ | 262 | */ |
149 | ldr r2,=0x00000000 | 263 | ldr r2, =0x00000000 |
150 | str r2, [r1, #8] | 264 | str r2, [r1, #0x08] |
151 | 265 | ||
152 | /* BANKCON2 | 266 | /* BANKCON2 |
153 | * Pagemode: normal (1 data) 00 | 267 | * Pagemode: normal (1 data) 00 |
@@ -158,17 +272,17 @@ start: | |||
158 | * Chip select setup time: 4 clocks 11 | 272 | * Chip select setup time: 4 clocks 11 |
159 | * Address setup time: 0 clocks 00 | 273 | * Address setup time: 0 clocks 00 |
160 | */ | 274 | */ |
161 | ldr r2,=0x00001FA0 | 275 | ldr r2, =0x00001FA0 |
162 | str r2, [r1, #0xC] | 276 | str r2, [r1, #0xC] |
163 | 277 | ||
164 | /* BANKCON3 */ | 278 | /* BANKCON3 */ |
165 | ldr r2,=0x00001D80 | 279 | ldr r2, =0x00001D80 |
166 | str r2, [r1, #0x10] | 280 | str r2, [r1, #0x10] |
167 | /* BANKCON4 */ | 281 | /* BANKCON4 */ |
168 | str r2, [r1, #0x14] | 282 | str r2, [r1, #0x14] |
169 | 283 | ||
170 | /* BANKCON5 */ | 284 | /* BANKCON5 */ |
171 | ldr r2,=0x00000000 | 285 | ldr r2, =0x00000000 |
172 | str r2, [r1, #0x18] | 286 | str r2, [r1, #0x18] |
173 | 287 | ||
174 | /* BANKCON6/7 | 288 | /* BANKCON6/7 |
@@ -181,13 +295,13 @@ start: | |||
181 | * Tacs: 0 clock 00 | 295 | * Tacs: 0 clock 00 |
182 | * MT: Sync DRAM 11 | 296 | * MT: Sync DRAM 11 |
183 | */ | 297 | */ |
184 | ldr r2,=0x00018005 | 298 | ldr r2, =0x00018005 |
185 | str r2, [r1, #0x1C] | 299 | str r2, [r1, #0x1C] |
186 | /* BANKCON7 */ | 300 | /* BANKCON7 */ |
187 | str r2, [r1, #0x20] | 301 | str r2, [r1, #0x20] |
188 | 302 | ||
189 | /* REFRESH */ | 303 | /* REFRESH */ |
190 | ldr r2,=0x00980501 | 304 | ldr r2, =0x00980501 |
191 | str r2, [r1, #0x24] | 305 | str r2, [r1, #0x24] |
192 | 306 | ||
193 | /* BANKSIZE | 307 | /* BANKSIZE |
@@ -198,117 +312,158 @@ start: | |||
198 | * Reserved: 0 0 | 312 | * Reserved: 0 0 |
199 | * BURST_EN: enabled 1 | 313 | * BURST_EN: enabled 1 |
200 | */ | 314 | */ |
201 | ldr r2,=0x00000090 | 315 | ldr r2, =0x00000090 |
202 | str r2, [r1, #0x28] | 316 | str r2, [r1, #0x28] |
203 | 317 | ||
204 | /* MRSRB6 */ | 318 | /* MRSRB6 */ |
205 | ldr r2,=0x00000030 | 319 | ldr r2, =0x00000030 |
206 | str r2, [r1, #0x2C] | 320 | str r2, [r1, #0x2C] |
207 | /* MRSRB7 */ | 321 | /* MRSRB7 */ |
208 | str r2, [r1, #0x30] | 322 | str r2, [r1, #0x30] |
209 | 323 | ||
210 | #if 0 | 324 | #if 0 |
211 | /* This next part I am not sure of the purpose */ | ||
212 | |||
213 | /* GPACON */ | 325 | /* GPACON */ |
214 | mov r2,#0x01FFFCFF | 326 | mov r1, #0x56000000 |
215 | str r2,=0x56000000 | 327 | ldr r2, =0x01FFFCFF /* 0x01FFFCFF */ |
328 | str r2, [r1] | ||
216 | 329 | ||
217 | /* GPADAT */ | 330 | /* GPADAT */ |
218 | mov r2,#0x01FFFEFF | 331 | ldr r2, =0x01FFFEFF |
219 | str r2,=0x56000004 | 332 | str r2, [r1, #0x04] |
220 | 333 | ||
221 | /* MRSRB6 */ | 334 | /* MRSRB6 */ |
222 | mov r2,#0x00000000 | 335 | mov r1, #0x48000000 |
223 | str r2,=0x4800002C | 336 | mov r2, #0x00000000 |
337 | str r2, [r1, #0x2C] | ||
224 | 338 | ||
225 | /* GPADAT */ | 339 | /* GPADAT */ |
226 | ldr r2,=0x01FFFFFF | 340 | mov r1, #0x56000000 |
227 | mov r1, #0x56000000 | 341 | ldr r2, =0x01FFFFFF |
228 | str r2, [r1, #4] | 342 | str r2, [r1, #0x04] |
229 | 343 | ||
230 | /* MRSRB6 */ | 344 | /* MRSRB6 */ |
231 | mov r2,#0x00000030 | 345 | mov r1, #0x48000000 |
232 | str r2,=0x4800002C | 346 | mov r2, #0x00000030 |
347 | str r2, [r1, #0x2C] | ||
233 | 348 | ||
234 | /* GPACON */ | 349 | /* GPACON */ |
235 | mov r2,#0x01FFFFFF | 350 | mov r1, #0x56000000 |
236 | str r2,=0x56000000 | 351 | mov r2, #0x01FFFFFF |
352 | str r2, [r1] | ||
237 | 353 | ||
238 | /* End of the unknown */ | 354 | /* End of the unknown */ |
239 | #endif | 355 | #endif |
240 | 356 | ||
241 | /* get the high part of our execute address */ | 357 | /* The builds have two potential load addresses, one being from flash, |
242 | ldr r2, =0xffffff00 | 358 | * and the other from some "unknown" location right now the assumption |
243 | and r4, pc, r2 | 359 | * is that the code is not at 0x3000000. |
244 | 360 | */ | |
245 | /* Copy bootloader to safe area - 0x31000000 */ | 361 | /* get the high part of our execute address (where am I) */ |
246 | mov r5, #0x30000000 | 362 | ldr r0, =0xfffff000 |
247 | add r5, r5, #0x1000000 | 363 | and r0, pc, r0 |
248 | ldr r6, = _dataend | 364 | |
249 | sub r0, r6, r5 /* length of loader */ | 365 | /* Copy code to 0x30000000 */ |
250 | add r0, r4, r0 /* r0 points to start of loader */ | 366 | ldr r2, = _vectorstart |
251 | 1: | 367 | ldr r3, = _iramend |
252 | cmp r5, r6 | 368 | |
253 | ldrcc r2, [r4], #4 | 369 | sub r2, r3, r2 /* length of loader */ |
254 | strcc r2, [r5], #4 | 370 | |
255 | bcc 1b | 371 | ldr r1, =0x30000000 /* copy location */ |
256 | |||
257 | ldr pc, =start_loc /* jump to the relocated start_loc: */ | ||
258 | 372 | ||
259 | start_loc: | 373 | bl word_copy |
260 | bl main | 374 | |
375 | ldr r1, =donecopy | ||
376 | ldr r2, =0x30000000 | ||
377 | add r1, r1, r2 | ||
378 | mov pc, r1 /* The code is located where we want it-jump*/ | ||
379 | |||
380 | donecopy: | ||
381 | |||
382 | /* Setup the MMU, start by disabling */ | ||
261 | 383 | ||
262 | #else /* BOOTLOADER */ | 384 | mrc p15, 0, r0, c1, c0, 0 |
385 | bic r0, r0, #0x41 /* disable mmu and dcache */ | ||
386 | bic r0, r0, #0x1000 /* disable icache */ | ||
387 | mcr p15, 0, r0, c1, c0, 0 | ||
388 | |||
389 | bl ttb_init | ||
390 | |||
391 | ldr r0, =0x0 | ||
392 | ldr r1, =0x0 | ||
393 | ldr r2, =0x1000 | ||
394 | mov r3, #0 | ||
395 | bl map_section | ||
396 | |||
397 | ldr r0, =0x30000000 | ||
398 | ldr r1, =0x0 | ||
399 | mov r2, #32 | ||
400 | mov r3, #12 | ||
401 | bl map_section | ||
402 | |||
403 | ldr r0, =0x31FD6800 /* FRAME */ | ||
404 | mov r1, r0 | ||
405 | mov r2, #1 | ||
406 | mov r3, #4 | ||
407 | bl map_section | ||
408 | |||
409 | bl enable_mmu | ||
410 | |||
411 | /* Zero out IBSS */ | ||
412 | ldr r2, =_iedata | ||
413 | ldr r3, =_iend | ||
414 | mov r4, #0 | ||
415 | ibsszero: | ||
416 | cmp r3, r2 | ||
417 | strhi r4, [r2], #4 | ||
418 | bhi ibsszero | ||
419 | |||
420 | /* Copy the IRAM */ | ||
421 | ldr r0, =_iramcopy | ||
422 | ldr r1, =_iramstart | ||
423 | ldr r2, =_iramend | ||
424 | sub r2, r2, r1 | ||
425 | bl word_copy | ||
426 | |||
427 | /* Initialise bss section to zero */ | ||
428 | ldr r2, =_edata | ||
429 | ldr r3, =_end | ||
430 | mov r4, #0 | ||
431 | bsszero: | ||
432 | cmp r3, r2 | ||
433 | strhi r4, [r2], #4 | ||
434 | bhi bsszero | ||
435 | |||
436 | /* Set up some stack and munge it with 0xdeadbeef */ | ||
437 | ldr sp, =stackend | ||
438 | mov r3, sp | ||
439 | ldr r2, =stackbegin | ||
440 | ldr r4, =0xdeadbeef | ||
441 | stackmunge: | ||
442 | cmp r3, r2 | ||
443 | strhi r4, [r2], #4 | ||
444 | bhi stackmunge | ||
263 | 445 | ||
264 | /* Set up stack for IRQ mode */ | 446 | /* Set up stack for IRQ mode */ |
265 | msr cpsr_c, #0xd2 | 447 | msr cpsr_c, #0xd2 |
266 | ldr sp, =irq_stack | 448 | ldr sp, =irq_stack |
267 | /* Set up stack for FIQ mode */ | 449 | /* Set up stack for FIQ mode */ |
268 | msr cpsr_c, #0xd1 | 450 | msr cpsr_c, #0xd1 |
269 | ldr sp, =fiq_stack | 451 | ldr sp, =fiq_stack |
270 | 452 | ||
271 | /* Let abort and undefined modes use IRQ stack */ | 453 | /* Let abort and undefined modes use IRQ stack */ |
272 | msr cpsr_c, #0xd7 | 454 | msr cpsr_c, #0xd7 |
273 | ldr sp, =irq_stack | 455 | ldr sp, =irq_stack |
274 | msr cpsr_c, #0xdb | 456 | msr cpsr_c, #0xdb |
275 | ldr sp, =irq_stack | 457 | ldr sp, =irq_stack |
276 | /* Switch to supervisor mode */ | 458 | /* Switch to supervisor mode */ |
277 | msr cpsr_c, #0xd3 | 459 | msr cpsr_c, #0xd3 |
278 | ldr sp, =stackend | 460 | ldr sp, =stackend |
279 | bl main | 461 | |
280 | /* main() should never return */ | 462 | /* Start the main function */ |
281 | 463 | ldr pc, =main | |
282 | /* Exception handlers. Will be copied to address 0 after memory remapping */ | 464 | |
283 | .section .vectors,"aw" | 465 | /* Should never get here, but let's restart in case */ |
284 | ldr pc, [pc, #24] | 466 | // b vectors |
285 | ldr pc, [pc, #24] | ||
286 | ldr pc, [pc, #24] | ||
287 | ldr pc, [pc, #24] | ||
288 | ldr pc, [pc, #24] | ||
289 | ldr pc, [pc, #24] | ||
290 | ldr pc, [pc, #24] | ||
291 | ldr pc, [pc, #24] | ||
292 | |||
293 | /* Exception vectors */ | ||
294 | .global vectors | ||
295 | vectors: | ||
296 | .word start | ||
297 | .word undef_instr_handler | ||
298 | .word software_int_handler | ||
299 | .word prefetch_abort_handler | ||
300 | .word data_abort_handler | ||
301 | .word reserved_handler | ||
302 | .word irq_handler | ||
303 | .word fiq_handler | ||
304 | |||
305 | .text | ||
306 | |||
307 | #ifndef STUB | ||
308 | .global irq | ||
309 | .global fiq | ||
310 | .global UIE | ||
311 | #endif | ||
312 | 467 | ||
313 | /* All illegal exceptions call into UIE with exception address as first | 468 | /* All illegal exceptions call into UIE with exception address as first |
314 | parameter. This is calculated differently depending on which exception | 469 | parameter. This is calculated differently depending on which exception |
@@ -337,11 +492,15 @@ data_abort_handler: | |||
337 | mov r1, #2 | 492 | mov r1, #2 |
338 | b UIE | 493 | b UIE |
339 | 494 | ||
340 | #ifdef STUB | 495 | #if defined(BOOTLOADER) |
341 | UIE: | 496 | fiq_handler: |
342 | b UIE | 497 | b UIE |
343 | #endif | 498 | #endif |
344 | 499 | ||
500 | UIE: | ||
501 | b UIE | ||
502 | |||
503 | .section .text | ||
345 | /* 256 words of IRQ stack */ | 504 | /* 256 words of IRQ stack */ |
346 | .space 256*4 | 505 | .space 256*4 |
347 | irq_stack: | 506 | irq_stack: |
@@ -350,4 +509,3 @@ irq_stack: | |||
350 | .space 256*4 | 509 | .space 256*4 |
351 | fiq_stack: | 510 | fiq_stack: |
352 | 511 | ||
353 | #endif /* BOOTLOADER */ | ||