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-rw-r--r--firmware/target/arm/s3c2440/crt0.S291
1 files changed, 187 insertions, 104 deletions
diff --git a/firmware/target/arm/s3c2440/crt0.S b/firmware/target/arm/s3c2440/crt0.S
index d18c2550e4..b8cb9f3908 100644
--- a/firmware/target/arm/s3c2440/crt0.S
+++ b/firmware/target/arm/s3c2440/crt0.S
@@ -26,6 +26,149 @@
26#include "config.h" 26#include "config.h"
27#include "cpu.h" 27#include "cpu.h"
28 28
29/****************************************************************************/
30#ifdef TOSHIBA_GIGABEAT_F
31
32/* Clock and Power Management setup values */
33#define VAL_CLKDIV 0x7
34#define VAL_UPLLCON 0x0003C042
35#define VAL_MPLLCON 0x000C9042
36
37/* Memory Controller setup */
38 /* Memory setup (taken from 0x5070) */
39 /* BWSCON
40 * Reserved 0
41 * Bank 0:
42 * Bus width 01 (16 bit)
43 * Bank 1:
44 * Buswidth 00 (8 bit)
45 * Disable wait 0
46 * Not using UB/LB 0
47 * Bank 2:
48 * Buswidth 10 (32 bit)
49 * Disable wait 0
50 * Not using UB/LB 0
51 * Bank 3:
52 * Buswidth 10 (32 bit)
53 * Disable wait 0
54 * Use UB/LB 1
55 * Bank 4:
56 * Buswidth 10 (32 bit)
57 * Disable wait 0
58 * Use UB/LB 1
59 * Bank 5:
60 * Buswidth 00 (8 bit)
61 * Disable wait 0
62 * Not using UB/LB 0
63 * Bank 6:
64 * Buswidth 10 (32 bit)
65 * Disable wait 0
66 * Not using UB/LB 0
67 * Bank 7:
68 * Buswidth 00 (8 bit)
69 * Disable wait 0
70 * Not using UB/LB 0
71 */
72#define VAL_BWSCON 0x01055102
73 /* BANKCON0
74 * Pagemode: normal (1 data) 00
75 * Pagemode access cycle: 2 clocks 00
76 * Address hold: 2 clocks 10
77 * Chip selection hold time: 1 clock 10
78 * Access cycle: 8 clocks 101
79 * Chip select setup time: 1 clock 01
80 * Address setup time: 0 clock 00
81 */
82#define VAL_BANKCON0 0x00000D60
83 /* BANKCON1
84 * Pagemode: normal (1 data) 00
85 * Pagemode access cycle: 2 clocks 00
86 * Address hold: 0 clocks 00
87 * Chip selection hold time: 0 clock 00
88 * Access cycle: 1 clocks 000
89 * Chip select setup time: 0 clocks 00
90 * Address setup time: 0 clocks 00
91 */
92#define VAL_BANKCON1 0x00000000
93 /* BANKCON2
94 * Pagemode: normal (1 data) 00
95 * Pagemode access cycle: 2 clocks 00
96 * Address hold: 2 clocks 10
97 * Chip selection hold time: 2 clocks 10
98 * Access cycle: 14 clocks 111
99 * Chip select setup time: 4 clocks 11
100 * Address setup time: 0 clocks 00
101 */
102#define VAL_BANKCON2 0x00001FA0
103#define VAL_BANKCON3 0x00001D80
104#define VAL_BANKCON4 0x00001D80
105#define VAL_BANKCON5 0x00000000
106 /* BANKCON6/7
107 * SCAN: 9 bit 01
108 * Trcd: 3 clocks 01
109 * Tcah: 0 clock 00
110 * Tcoh: 0 clock 00
111 * Tacc: 1 clock 000
112 * Tcos: 0 clock 00
113 * Tacs: 0 clock 00
114 * MT: Sync DRAM 11
115 */
116#define VAL_BANKCON6 0x00018005
117#define VAL_BANKCON7 0x00018005
118
119#define VAL_REFRESH 0x00980501
120 /* BANKSIZE
121 * BK76MAP: 32M/32M 000
122 * Reserved: 0 0 (was 1)
123 * SCLK_EN: always 1 (was 0)
124 * SCKE_EN: disable 0
125 * Reserved: 0 0
126 * BURST_EN: enabled 1
127 */
128#define VAL_BANKSIZE 0x00000090
129#define VAL_MRSRB6 0x00000030
130#define VAL_MRSRB7 0x00000030
131#define VAL_GPACON 0x00FFFFFF
132
133/****************************************************************************/
134#elif defined (MINI2440)
135
136/* For Mini2440 board or compatible */
137/* Clock and Power Management setup values */
138#define VAL_CLKDIV 0x5 /* HCLK = FCLK/4, PCLK = HCLK/2 */
139#define VAL_UPLLCON 0x00038022 /* UCLK = 48 MHz */
140#define VAL_MPLLCON 0x0007F021 /* FCLK = 405 MHz */
141
142#define FCLK 405000000
143#define HCLK (FCLK/4) /* = 101,250,000 */
144#define PCLK (HCLK/2) /* = 50,625,000 */
145
146/* Memory Controller setup */
147#define VAL_BWSCON 0x22111112
148#define VAL_BANKCON0 0x00002F50
149#define VAL_BANKCON1 0x00000700
150#define VAL_BANKCON2 0x00000700
151#define VAL_BANKCON3 0x00000700
152#define VAL_BANKCON4 0x00000700
153#define VAL_BANKCON5 0x0007FFFC
154#define VAL_BANKCON6 0x00018009
155#define VAL_BANKCON7 0x00018009
156
157#define VAL_REFRESH 0x008E04EB
158#define VAL_BANKSIZE 0x000000B2
159#define VAL_MRSRB6 0x00000030
160#define VAL_MRSRB7 0x00000030
161
162#define VAL_GPACON 0x00FFFFFF
163#define VAL_GPFCON 0x000055AA
164#define VAL_GPGCON 0xAA2A0128
165#define VAL_GPGDAT 0x0000
166
167#else
168#error Unknown target
169#endif
170/****************************************************************************/
171
29/* Exception Handlers */ 172/* Exception Handlers */
30.section .vectors,"ax",%progbits 173.section .vectors,"ax",%progbits
31.code 32 174.code 32
@@ -73,6 +216,7 @@ word_copy:
73.ltorg 216.ltorg
74.size word_copy, .-word_copy 217.size word_copy, .-word_copy
75 218
219
76/* 220/*
77 * Entry: start 221 * Entry: start
78 * Variables: 222 * Variables:
@@ -95,6 +239,7 @@ start:
95 239
96 /************************** DO NOT WRITE TO R0 ***************************/ 240 /************************** DO NOT WRITE TO R0 ***************************/
97 241
242#ifdef TOSHIBA_GIGABEAT_F
98 /* Check if the code is running from flash. If not skip all these checks */ 243 /* Check if the code is running from flash. If not skip all these checks */
99 cmp r0, #0xA0000 244 cmp r0, #0xA0000
100 bne poweron 245 bne poweron
@@ -105,7 +250,6 @@ start:
105 str r1, [r2, #0x14] 250 str r1, [r2, #0x14]
106 251
107 /* Did an RTC event wake the player up? */ 252 /* Did an RTC event wake the player up? */
108
109 mov r2, #0x4A000000 253 mov r2, #0x4A000000
110 ldr r1, [r2] 254 ldr r1, [r2]
111 ands r1, r1, #0x40000000 255 ands r1, r1, #0x40000000
@@ -147,6 +291,7 @@ start:
147bootOF: 291bootOF:
148 /* power is not down || menu is held || the charger is not connected */ 292 /* power is not down || menu is held || the charger is not connected */
149 mov pc, #0x70 293 mov pc, #0x70
294#endif
150 295
151poweron: 296poweron:
152 /* enter supervisor mode, disable IRQ */ 297 /* enter supervisor mode, disable IRQ */
@@ -166,6 +311,7 @@ poweron:
166 ldr r2, =0x00003FFF 311 ldr r2, =0x00003FFF
167 str r2, [r1, #0x1C] 312 str r2, [r1, #0x1C]
168 313
314#ifdef TOSHIBA_GIGABEAT_F
169 /* Check if loaded by the old bootloader or by the OF. This copy routine 315 /* Check if loaded by the old bootloader or by the OF. This copy routine
170 * cannot run/copy properly until the memory has been initialized, so the 316 * cannot run/copy properly until the memory has been initialized, so the
171 * copy routine later is still necessary. The old bootloader/OF will 317 * copy routine later is still necessary. The old bootloader/OF will
@@ -198,6 +344,7 @@ poweron:
198 bl word_copy 344 bl word_copy
199 345
200 mov pc, #0x31000000 346 mov pc, #0x31000000
347#endif
201 348
202skipreset: 349skipreset:
203 350
@@ -209,7 +356,7 @@ skipreset:
209 orr r0, r0, r1 356 orr r0, r0, r1
210 mcr p15, 0, r0, c1, c0, 0 357 mcr p15, 0, r0, c1, c0, 0
211 358
212 mov r2, #0x7 359 mov r2, #VAL_CLKDIV
213 mov r1, #0x4C000000 360 mov r1, #0x4C000000
214 str r2, [r1, #0x14] 361 str r2, [r1, #0x14]
215 362
@@ -219,7 +366,7 @@ skipreset:
219 ldr r2, =0xFFFFFFFF 366 ldr r2, =0xFFFFFFFF
220 str r2, [r1] 367 str r2, [r1]
221 368
222 ldr r2, =0x0003C042 369 ldr r2, =VAL_UPLLCON
223 str r2, [r1, #0x08] 370 str r2, [r1, #0x08]
224 371
225 nop 372 nop
@@ -231,7 +378,7 @@ skipreset:
231 nop 378 nop
232 nop 379 nop
233 380
234 ldr r2, =0x000C9042 381 ldr r2, =VAL_MPLLCON
235 str r2, [r1, #0x04] 382 str r2, [r1, #0x04]
236 383
237 nop 384 nop
@@ -248,128 +395,55 @@ skipreset:
248 mov r1, #0x56000000 395 mov r1, #0x56000000
249 str r2, [r1, #0x80] 396 str r2, [r1, #0x80]
250 397
251 /* Memory setup (taken from 0x5070) */ 398 /* Memory setup */
252 399
253 /* BWSCON 400 ldr r2, =VAL_BWSCON
254 * Reserved 0
255 * Bank 0:
256 * Bus width 01 (16 bit)
257 * Bank 1:
258 * Buswidth 00 (8 bit)
259 * Disable wait 0
260 * Not using UB/LB 0
261 * Bank 2:
262 * Buswidth 10 (32 bit)
263 * Disable wait 0
264 * Not using UB/LB 0
265 * Bank 3:
266 * Buswidth 10 (32 bit)
267 * Disable wait 0
268 * Use UB/LB 1
269 * Bank 4:
270 * Buswidth 10 (32 bit)
271 * Disable wait 0
272 * Use UB/LB 1
273 * Bank 5:
274 * Buswidth 00 (8 bit)
275 * Disable wait 0
276 * Not using UB/LB 0
277 * Bank 6:
278 * Buswidth 10 (32 bit)
279 * Disable wait 0
280 * Not using UB/LB 0
281 * Bank 7:
282 * Buswidth 00 (8 bit)
283 * Disable wait 0
284 * Not using UB/LB 0
285 */
286 ldr r2, =0x01055102
287 mov r1, #0x48000000 401 mov r1, #0x48000000
288 str r2, [r1] 402 str r2, [r1]
289 403
290 /* BANKCON0 404 /* BANKCON0 */
291 * Pagemode: normal (1 data) 00 405 ldr r2, =VAL_BANKCON0
292 * Pagemode access cycle: 2 clocks 00
293 * Address hold: 2 clocks 10
294 * Chip selection hold time: 1 clock 10
295 * Access cycle: 8 clocks 101
296 * Chip select setup time: 1 clock 01
297 * Address setup time: 0 clock 00
298 */
299 ldr r2, =0x00000D60
300 str r2, [r1, #0x04] 406 str r2, [r1, #0x04]
301 407
302 408 /* BANKCON1 */
303 /* BANKCON1 409 ldr r2, =VAL_BANKCON1
304 * Pagemode: normal (1 data) 00
305 * Pagemode access cycle: 2 clocks 00
306 * Address hold: 0 clocks 00
307 * Chip selection hold time: 0 clock 00
308 * Access cycle: 1 clocks 000
309 * Chip select setup time: 0 clocks 00
310 * Address setup time: 0 clocks 00
311 */
312 ldr r2, =0x00000000
313 str r2, [r1, #0x08] 410 str r2, [r1, #0x08]
314 411
315 /* BANKCON2 412 /* BANKCON2 */
316 * Pagemode: normal (1 data) 00 413 ldr r2, =VAL_BANKCON2
317 * Pagemode access cycle: 2 clocks 00
318 * Address hold: 2 clocks 10
319 * Chip selection hold time: 2 clocks 10
320 * Access cycle: 14 clocks 111
321 * Chip select setup time: 4 clocks 11
322 * Address setup time: 0 clocks 00
323 */
324 ldr r2, =0x00001FA0
325 str r2, [r1, #0xC] 414 str r2, [r1, #0xC]
326 415
327 /* BANKCON3 */ 416 /* BANKCON3 */
328 ldr r2, =0x00001D80 417 ldr r2, =VAL_BANKCON3
329 str r2, [r1, #0x10] 418 str r2, [r1, #0x10]
330 /* BANKCON4 */ 419 /* BANKCON4 */
331 str r2, [r1, #0x14] 420 str r2, [r1, #0x14]
332 421
333 /* BANKCON5 */ 422 /* BANKCON5 */
334 ldr r2, =0x00000000 423 ldr r2, =VAL_BANKCON5
335 str r2, [r1, #0x18] 424 str r2, [r1, #0x18]
336 425
337 /* BANKCON6/7 426 /* BANKCON6/7 */
338 * SCAN: 9 bit 01 427 ldr r2, =VAL_BANKCON6
339 * Trcd: 3 clocks 01
340 * Tcah: 0 clock 00
341 * Tcoh: 0 clock 00
342 * Tacc: 1 clock 000
343 * Tcos: 0 clock 00
344 * Tacs: 0 clock 00
345 * MT: Sync DRAM 11
346 */
347 ldr r2, =0x00018005
348 str r2, [r1, #0x1C] 428 str r2, [r1, #0x1C]
349 /* BANKCON7 */ 429 /* BANKCON7 */
350 str r2, [r1, #0x20] 430 str r2, [r1, #0x20]
351 431
352 /* REFRESH */ 432 /* REFRESH */
353 ldr r2, =0x00980501 433 ldr r2, =VAL_REFRESH
354 str r2, [r1, #0x24] 434 str r2, [r1, #0x24]
355 435
356 /* BANKSIZE 436 /* BANKSIZE */
357 * BK76MAP: 32M/32M 000 437 ldr r2, =VAL_BANKSIZE
358 * Reserved: 0 0 (was 1)
359 * SCLK_EN: always 1 (was 0)
360 * SCKE_EN: disable 0
361 * Reserved: 0 0
362 * BURST_EN: enabled 1
363 */
364 ldr r2, =0x00000090
365 str r2, [r1, #0x28] 438 str r2, [r1, #0x28]
366 439
367 /* MRSRB6 */ 440 /* MRSRB6 */
368 ldr r2, =0x00000030 441 ldr r2, =VAL_MRSRB6
369 str r2, [r1, #0x2C] 442 str r2, [r1, #0x2C]
370 /* MRSRB7 */ 443 /* MRSRB7 */
371 str r2, [r1, #0x30] 444 str r2, [r1, #0x30]
372 445
446 /* RMC: I guess this is some notes about Gigabeat */
373 /* 447 /*
374 0x56000000 0x1FFFCFF 448 0x56000000 0x1FFFCFF
375 4 0x1FFFEFF 449 4 0x1FFFEFF
@@ -379,25 +453,33 @@ skipreset:
379 453
380 /* GPACON */ 454 /* GPACON */
381 mov r1, #0x56000000 455 mov r1, #0x56000000
382 ldr r2, =0x00FFFFFF 456 ldr r2, =VAL_GPACON
383 str r2, [r1] 457 str r2, [r1]
384 458
385 /* The builds have two potential load addresses, one being from flash, 459#if 0
460 /* GPGCON */
461 ldr r2, =VAL_GPGCON
462 str r2, [r1, #0x60]
463 ldr r2, =VAL_GPGDAT
464 str r2, [r1, #0x64]
465#endif
466
467 /* Copy from current location (from NOR Flash if bootloader, load buffer if
468 firmware) to RAM */
469
470 /* Gigabeat: The builds have two potential load addresses, one being from flash,
386 * and the other from some "unknown" location right now the assumption 471 * and the other from some "unknown" location right now the assumption
387 * is that the code is not at 0x3000000. 472 * is that the code is not at 0x3000000.
388 */ 473 */
389 /* get the high part of our execute address (where am I) */ 474 /* get the high part of our execute address (where am I) */
390 ldr r0, =0xfffff000 475 ldr r0, =0xfffff000
391 and r0, pc, r0 476 and r0, pc, r0 /* copy from address */
392 477
393 /* Copy code to 0x30000000 */ 478 /* SDRAM starts at 0x30000000 (physical address) */
479 ldr r1, =0x30000000 /* copy To address */
394 ldr r2, = _vectorstart 480 ldr r2, = _vectorstart
395 ldr r3, = _initdata_end 481 ldr r3, = _initdata_end
396
397 sub r2, r3, r2 /* length of loader */ 482 sub r2, r3, r2 /* length of loader */
398
399 ldr r1, =0x30000000 /* copy location */
400
401 bl word_copy 483 bl word_copy
402 484
403 ldr r1, =donecopy 485 ldr r1, =donecopy
@@ -410,8 +492,8 @@ donecopy:
410 /* Setup the MMU, start by disabling */ 492 /* Setup the MMU, start by disabling */
411 493
412 mrc p15, 0, r0, c1, c0, 0 494 mrc p15, 0, r0, c1, c0, 0
413 bic r0, r0, #0x41 /* disable mmu and dcache */ 495 bic r0, r0, #0x41 /* disable mmu and dcache */
414 bic r0, r0, #0x1000 /* disable icache */ 496 bic r0, r0, #0x1000 /* disable icache */
415 mcr p15, 0, r0, c1, c0, 0 497 mcr p15, 0, r0, c1, c0, 0
416 498
417 bl ttb_init 499 bl ttb_init
@@ -515,6 +597,7 @@ fiq_handler:
515UIE: 597UIE:
516 b UIE 598 b UIE
517 599
600/* TODO: Review this function - is it target dependent? */
518/* 601/*
519 * Function: rom_shutdown 602 * Function: rom_shutdown
520 * Variables: 603 * Variables:
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-07 17:52:27 +0000