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Diffstat (limited to 'firmware/target/arm/rk27xx/system-rk27xx.c')
-rw-r--r--firmware/target/arm/rk27xx/system-rk27xx.c24
1 files changed, 17 insertions, 7 deletions
diff --git a/firmware/target/arm/rk27xx/system-rk27xx.c b/firmware/target/arm/rk27xx/system-rk27xx.c
index 8c75deef07..27373207bd 100644
--- a/firmware/target/arm/rk27xx/system-rk27xx.c
+++ b/firmware/target/arm/rk27xx/system-rk27xx.c
@@ -200,19 +200,29 @@ void udelay(unsigned usecs)
200 ); 200 );
201} 201}
202 202
203void commit_discard_idcache(void) 203/* Invalidating both cache lines from single function
204 * gives sometimes strange data aborts.
205 * This version resembles how OF invalidates cache.
206 * noinline attribute is to guarantee that future
207 * gcc change will not decide to inline this call (although
208 * current arm-eabi version from our toolchain doesn't do that
209 */
210static void __attribute__((noinline)) cache_invalidate_way(int way)
204{ 211{
205 /* invalidate cache way 0 */ 212 /* Issue invalidata way command to the cache controler */
206 CACHEOP = 0x02; 213 CACHEOP = ((way<<31)|0x2);
207 214
208 /* wait for invalidate process to complete */ 215 /* wait for invalidate process to complete */
209 while (CACHEOP & 0x03); 216 while (CACHEOP & 0x03);
217}
210 218
211 /* invalidate cache way 1 */ 219void commit_discard_idcache(void)
212 CACHEOP = 0x80000002; 220{
221 /* invalidate cache way 0 */
222 cache_invalidate_way(0);
213 223
214 /* wait for invalidate process to complete */ 224 /* invalidate cache way 1 */
215 while (CACHEOP & 0x03); 225 cache_invalidate_way(1);
216} 226}
217void commit_discard_dcache (void) __attribute__((alias("commit_discard_idcache"))); 227void commit_discard_dcache (void) __attribute__((alias("commit_discard_idcache")));
218 228