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Diffstat (limited to 'firmware/target/arm/rk27xx/crt0.S')
-rw-r--r--firmware/target/arm/rk27xx/crt0.S81
1 files changed, 44 insertions, 37 deletions
diff --git a/firmware/target/arm/rk27xx/crt0.S b/firmware/target/arm/rk27xx/crt0.S
index 23f3fcf2c9..1bbd46a12c 100644
--- a/firmware/target/arm/rk27xx/crt0.S
+++ b/firmware/target/arm/rk27xx/crt0.S
@@ -5,7 +5,6 @@
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/ 7 * \/ \/ \/ \/ \/
8 * $Id: crt0.S 18776 2008-10-11 18:32:17Z gevaerts $
9 * 8 *
10 * Copyright (C) 2008 by Marcoen Hirschberg 9 * Copyright (C) 2008 by Marcoen Hirschberg
11 * Copyright (C) 2008 by Denes Balatoni 10 * Copyright (C) 2008 by Denes Balatoni
@@ -24,26 +23,50 @@
24#include "config.h" 23#include "config.h"
25#include "cpu.h" 24#include "cpu.h"
26 25
27 .section .intvect,"ax",%progbits 26 .global start
28 .global start 27 .global entry_point
29 .global _newstart 28
30 /* Exception vectors */ 29 /* Exception vectors */
31start: 30 .section .intvect,"ax",%progbits
32 b _newstart 31 ldr pc, =start
33 ldr pc, =undef_instr_handler 32 ldr pc, =undef_instr_handler
34 ldr pc, =software_int_handler 33 ldr pc, =software_int_handler
35 ldr pc, =prefetch_abort_handler 34 ldr pc, =prefetch_abort_handler
36 ldr pc, =data_abort_handler 35 ldr pc, =data_abort_handler
37 ldr pc, =reserved_handler 36 ldr pc, =reserved_handler
38 ldr pc, =irq_handler 37 ldr pc, =irq_handler
39 ldr pc, =fiq_handler 38 ldr pc, =fiq_handler
40 .ltorg 39 .ltorg
41_newstart:
42 ldr pc, =newstart2
43 .section .init.text,"ax",%progbits
44newstart2:
45 msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
46 40
41 .text
42start:
43 msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
44
45#ifdef BOOTLOADER
46 sub r4, pc, #12 /* copy running address, accomodate
47 * for prefetch (-8) and msr instr (-4)
48 */
49
50 ldr r0, =0xefff0000 /* cache controler base address */
51 ldrh r1, [r0]
52 strh r1, [r0] /* global cache disable */
53
54 ldr r2, =_relocstart
55 ldr r3, =_relocend
56
57 cmp r2, r4
58 beq entry_point /* skip copying if we are in place already */
591:
60 cmp r3, r2
61 ldrhi r1, [r4], #4
62 strhi r1, [r2], #4
63 bhi 1b
64
65entry_point_jmp:
66 ldr pc, =entry_point
67#endif
68
69entry_point:
47 mov r0, #0x18000000 70 mov r0, #0x18000000
48 add r0, r0, #0x1c000 71 add r0, r0, #0x1c000
49 72
@@ -135,26 +158,14 @@ newstart2:
135 strhi r4, [r2], #4 158 strhi r4, [r2], #4
136 bhi 1b 159 bhi 1b
137 160
138#ifndef BOOTLOADER 161 /* Initialise bss, ibss section to zero */
139 /* Copy icode and data to ram */ 162 ldr r2, =_edata
140 ldr r2, =_iramstart 163 ldr r3, =_end
141 ldr r3, =_iramend
142 ldr r4, =_iramcopy
1431:
144 cmp r3, r2
145 ldrhi r1, [r4], #4
146 strhi r1, [r2], #4
147 bhi 1b
148
149 /* Initialise ibss section to zero */
150 ldr r2, =_iedata
151 ldr r3, =_iend
152 mov r4, #0 164 mov r4, #0
1531: 1651:
154 cmp r3, r2 166 cmp r3, r2
155 strhi r4, [r2], #4 167 strhi r4, [r2], #4
156 bhi 1b 168 bhi 1b
157#endif
158 169
159 /* Set up stack for IRQ mode */ 170 /* Set up stack for IRQ mode */
160 msr cpsr_c, #0xd2 171 msr cpsr_c, #0xd2
@@ -184,12 +195,8 @@ newstart2:
184 strhi r3, [r2], #4 195 strhi r3, [r2], #4
185 bhi 1b 196 bhi 1b
186 197
187
188 bl main 198 bl main
189 199
190 .text
191/* .global UIE*/
192
193/* All illegal exceptions call into UIE with exception address as first 200/* All illegal exceptions call into UIE with exception address as first
194 * parameter. This is calculated differently depending on which exception 201 * parameter. This is calculated differently depending on which exception
195 * we're in. Second parameter is exception number, used for a string lookup 202 * we're in. Second parameter is exception number, used for a string lookup