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Diffstat (limited to 'firmware/target/arm/pp')
-rw-r--r--firmware/target/arm/pp/app-pp.lds199
-rw-r--r--firmware/target/arm/pp/boot-pp.lds92
2 files changed, 291 insertions, 0 deletions
diff --git a/firmware/target/arm/pp/app-pp.lds b/firmware/target/arm/pp/app-pp.lds
new file mode 100644
index 0000000000..e6c2b255dd
--- /dev/null
+++ b/firmware/target/arm/pp/app-pp.lds
@@ -0,0 +1,199 @@
1/* Will have been included from app.lds */
2ENTRY(start)
3
4OUTPUT_FORMAT(elf32-littlearm)
5OUTPUT_ARCH(arm)
6STARTUP(target/arm/pp/crt0-pp.o)
7
8#define PLUGINSIZE PLUGIN_BUFFER_SIZE
9#define CODECSIZE CODEC_SIZE
10
11#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
12
13#define DRAMORIG 0x00000000
14#define IRAMORIG 0x40000000
15#define IRAMSIZE 0xc000
16
17#ifdef CPU_PP502x
18#define NOCACHE_BASE 0x10000000
19#else
20#define NOCACHE_BASE 0x28000000
21#endif
22
23#define CACHEALIGN_SIZE 16
24
25/* End of the audio buffer, where the codec buffer starts */
26#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
27
28/* Where the codec buffer ends, and the plugin buffer starts */
29#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
30
31MEMORY
32{
33 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
34 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
35}
36
37SECTIONS
38{
39 .text :
40 {
41 loadaddress = .;
42 _loadaddress = .;
43 . = ALIGN(0x200);
44 *(.init.text)
45 *(.text*)
46 *(.glue_7)
47 *(.glue_7t)
48 . = ALIGN(0x4);
49 } > DRAM
50
51 .rodata :
52 {
53 *(.rodata) /* problems without this, dunno why */
54 *(.rodata*)
55 *(.rodata.str1.1)
56 *(.rodata.str1.4)
57 . = ALIGN(0x4);
58 } > DRAM
59
60 .data :
61 {
62 *(.data*)
63 . = ALIGN(0x4);
64 } > DRAM
65
66#if NOCACHE_BASE != 0
67 /* .ncdata section is placed at uncached physical alias address and is
68 * loaded at the proper cached virtual address - no copying is
69 * performed in the init code */
70 .ncdata . + NOCACHE_BASE :
71 {
72 . = ALIGN(CACHEALIGN_SIZE);
73 *(.ncdata*)
74 . = ALIGN(CACHEALIGN_SIZE);
75 } AT> DRAM
76#endif
77
78 /DISCARD/ :
79 {
80 *(.eh_frame)
81 }
82
83 .vectors 0x0 :
84 {
85 _vectorsstart = .;
86 KEEP(*(.vectors));
87 _vectorsend = .;
88 } AT> DRAM
89
90 _vectorscopy = LOADADDR(.vectors);
91 _noloaddram = LOADADDR(.vectors);
92
93 .ibss IRAMORIG (NOLOAD) :
94 {
95 _iedata = .;
96 *(.qharray)
97 *(.ibss*)
98 . = ALIGN(0x4);
99 _iend = .;
100 } > IRAM
101
102 .iram _iend :
103 {
104 _iramstart = .;
105 *(.icode*)
106 *(.irodata*)
107 *(.idata*)
108 . = ALIGN(0x4);
109 _iramend = .;
110 } > IRAM AT> DRAM
111
112 _iramcopy = LOADADDR(.iram);
113
114
115 .init ENDAUDIOADDR :
116 {
117 . = ALIGN(4);
118 _initstart = .;
119 *(.init*)
120 _initend = .;
121 } AT> DRAM
122
123 _initcopy = LOADADDR(.init);
124
125 .idle_stacks (NOLOAD) :
126 {
127 *(.idle_stacks)
128#if NUM_CORES > 1
129 cpu_idlestackbegin = .;
130 . += IDLE_STACK_SIZE;
131 cpu_idlestackend = .;
132#endif
133 cop_idlestackbegin = .;
134 . += IDLE_STACK_SIZE;
135 cop_idlestackend = .;
136 } > IRAM
137
138 .stack (NOLOAD) :
139 {
140 *(.stack)
141 stackbegin = .;
142 . += 0x2000;
143 stackend = .;
144 } > IRAM
145
146 /* .bss and .ncbss are treated as a single section to use one init loop to
147 * zero it - note "_edata" and "_end" */
148 .bss _noloaddram (NOLOAD) :
149 {
150 _edata = .;
151 *(.bss*)
152 *(COMMON)
153 . = ALIGN(0x4);
154 } > DRAM
155
156#if NOCACHE_BASE != 0
157 .ncbss . + NOCACHE_BASE (NOLOAD):
158 {
159 . = ALIGN(CACHEALIGN_SIZE);
160 *(.ncbss*)
161 . = ALIGN(CACHEALIGN_SIZE);
162 } AT> DRAM
163#endif
164
165 /* This will be aligned by preceding alignments */
166 .endaddr . - NOCACHE_BASE (NOLOAD) :
167 {
168 _end = .;
169 } > DRAM
170
171 .audiobuf (NOLOAD) :
172 {
173 _audiobuffer = .;
174 . = ALIGN(0x4);
175 audiobuffer = .;
176 } > DRAM
177
178 .audiobufend ENDAUDIOADDR (NOLOAD) :
179 {
180#ifdef IPOD_VIDEO
181 audiobufend_lds = .;
182#else
183 audiobufend = .;
184#endif
185 _audiobufend = .;
186 } > DRAM
187
188 .codec ENDAUDIOADDR (NOLOAD) :
189 {
190 codecbuf = .;
191 _codecbuf = .;
192 }
193
194 .plugin ENDADDR (NOLOAD) :
195 {
196 _pluginbuf = .;
197 pluginbuf = .;
198 }
199}
diff --git a/firmware/target/arm/pp/boot-pp.lds b/firmware/target/arm/pp/boot-pp.lds
new file mode 100644
index 0000000000..602c3bf7ab
--- /dev/null
+++ b/firmware/target/arm/pp/boot-pp.lds
@@ -0,0 +1,92 @@
1#include "config.h"
2
3ENTRY(start)
4OUTPUT_FORMAT(elf32-littlearm)
5OUTPUT_ARCH(arm)
6STARTUP(target/arm/pp/crt0-pp-bl.o)
7
8#define DRAMSIZE (MEMORYSIZE * 0x100000)
9
10#if CONFIG_CPU == PP6100
11#define DRAMORIG 0x10f00000
12#ifndef IRAMORIG
13#define IRAMORIG 0x40000000
14#endif
15#define IRAMSIZE 0x20000
16#define FLASHORIG 0x001f0000
17#define FLASHSIZE 2M
18#if CONFIG_CPU == PP5020
19#define DRAMORIG 0x10000000
20#define IRAMORIG 0x40000000
21#define IRAMSIZE 0x18000
22#define FLASHORIG 0x001f0000
23#define FLASHSIZE 2M
24#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
25#define DRAMORIG 0x10000000
26#ifndef IRAMORIG
27#define IRAMORIG 0x40000000
28#endif
29#define IRAMSIZE 0x20000
30#define FLASHORIG 0x001f0000
31#define FLASHSIZE 2M
32#elif CONFIG_CPU == PP5002
33#define DRAMORIG 0x28000000
34#define IRAMORIG 0x40000000
35#define IRAMSIZE 0x18000
36#define FLASHORIG 0x001f0000
37#define FLASHSIZE 2M
38#endif
39
40MEMORY
41{
42 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
43 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
44}
45
46SECTIONS
47{
48#ifdef SANSA_PP_ERASE
49 . = IRAMORIG+0x4000;
50#else
51 . = IRAMORIG;
52#endif
53
54 .text : {
55 *(.init.text)
56 *(.text*)
57 *(.glue_7)
58 *(.glue_7t)
59 } > IRAM
60
61 .data : {
62 *(.icode)
63 *(.irodata)
64 *(.idata)
65 *(.data*)
66 *(.ncdata*)
67 *(.rodata*)
68 _dataend = . ;
69 } > IRAM
70
71 .stack (NOLOAD) : {
72 *(.stack)
73 _stackbegin = .;
74 stackbegin = .;
75 . += 0x2000;
76 _stackend = .;
77 stackend = .;
78 } > IRAM
79
80 /* The bss section is too large for IRAM - we just move it 16MB into the
81 DRAM */
82
83 . = DRAMORIG;
84 .bss . + (16*1024*1024) (NOLOAD) : {
85 _edata = .;
86 *(.bss*);
87 *(.ibss);
88 *(COMMON)
89 *(.ncbss*);
90 _end = .;
91 } > DRAM
92}